PCAL9722 datasheet(21/63 Pages) NXP

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NXP Semiconductors

PCAL9722

Ultra low-voltage translating 22-bit SPI I/O expander with Agile I/O features, interrupt output and

reset

Bit

Symbol

II1.7

II1.6

II1.5

II1.4

II1.3

II1.2

II1.1

II1.0

Default

Table 52. Input status port 1 register (address 6Dh) bit description

Bit

Symbol

II2.7

II2.6

II2.5

II2.4

II2.3

II2.2

II2.1

II2.0

Default

0 (NA)

Table 53. Input status port 2 register (address 6Eh) bit description

6.4.15 Individual pin output configuration registers (70h, 71h, 72h)

The individual pin output configuration registers modify output configuration (push-pull or open-drain) set by the

Output Port Configuration register (5Ch).

If the ODENx bit is set at logic 0 (push-pull), any bit set to logic 1 in the IOCRx register will reverse the output

state of that pin only to open-drain. When ODENx bit is set at logic 1 (open-drain), a logic 1 in IOCRx will set

that pin to push-pull.

The recommended command sequence to program the output pin is to program ODENx (5Ch), the IOCRx, and

finally the Configuration register (0Ch, 0Dh, 0Eh) to set the pins as outputs. A register group write operation is

described in Section 7.3. A register group read operation is described in Section 7.5.

Bit

Symbol

IOCR0.7

IOCR0.6

IOCR0.5

IOCR0.4

IOCR0.3

IOCR0.2

IOCR0.1

IOCR0.0

Default

Table 54. Individual pin output configuration register 0 (address 70h) bit description

Bit

Symbol

IOCR1.7

IOCR1.6

IOCR1.5

IOCR1.4

IOCR1.3

IOCR1.2

IOCR1.1

IOCR1.0

Default

Table 55. Individual pin output configuration register 1 (address 71h) bit description

Bit

Symbol

IOCR2.7

IOCR2.6

IOCR2.5

IOCR2.4

IOCR2.3

IOCR2.2

IOCR2.1

IOCR2.0

Default

0 (NA)

Table 56. Individual pin output configuration register 2 (address 72h) bit description

6.4.16 Switch debounce enable registers (74h, 75h)

The switch debounce enable registers enable the switch debounce function for Port 0 and Port 1 pins. If a pin

on Port 0 or Port 1 is designated as an input, a logic 1 in the Switch debounce enable register will connect

debounce logic to that pin. If a pin is assigned as an output (via Configuration Port 0 or Port 1 register) the

debounce logic is not connected to that pin and it will function as a normal output. The switch debounce logic

PCAL9722

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 1 May 2023

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