FXLS8971CF datasheet(62/100 Pages) NXP

62 / 100 page

NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

Disabling the buffer clears the

BUF_STATUS[BUF_OVF] and BUF_STATUS[BUF_WMRK] event flags.

Disabling the buffer also clears the

BUF_STATUS[BUF_CNT] field. The SYS_MODE[BUF_GATE_ERR] and

SYS_MODE[buf_gate_cnt] fields are also reset when the buffer is disabled, flushed, or when the host reads out

all the content.

Notes for using triggered operating mode with Auto-WAKE/SLEEP mode enabled:

1. When BUF_MODE = 11b,

ASLP_COUNT ≥ 1, and the ACTIVE bit is set, FXLS8971CF immediately enters

the WAKE mode. After

ASLP_COUNT ODR periods, the buffer is flushed and the part enters SLEEP mode.

The buffer collects up to

BUF_CONFIG2[BUF_WMRK] samples at the SLEEP mode ODR before the trigger

event occurs (in stream mode).

2. After the trigger event, FXLS8971CF enters WAKE mode and remain there regardless of the setting made

ASLP_COUNT, ignore any subsequent triggers, and collects (32 - BUF_WMRK[5:0]) samples at the

WAKE mode ODR, set the BUF_OVF flag, and cease collecting more data until the host flushes the buffer

or reads out all of the contents. Once the buffer is emptied or flushed, the triggered mode is re-armed, but

FXLS8971CF must first re-enter SLEEP mode (which will happen after

ASLP_COUNT WAKE ODR periods)

before a second set of data can be collected.

3. The

BUF_CONFIG1[BUF_GATE] setting is ignored and has no effect. The buffer contents are automatically

flushed when FXLS8971CF transitions from WAKE to SLEEP.

4. The interrupt events that prevent FXLS8971CF from entering SLEEP mode also prevents the operation of

the triggered mode (which requires FXLS8971CF to first enter the SLEEP mode).

15.3.15 BUF_CONFIG2 register (address 27h)

Bit

Name

BUF_

FLUSH

WAKE_

SRC_BUF

BUF_WMRK[5:0]

Reset

Access

R/W

Table 80. BUF_CONFIG2 register (address 27h) bit allocation

Field

Description

BUF_FLUSH

Buffer flush enable:

0: No pending buffer flush operation, or buffer flush completed

1: Buffer flush enable: all buffer contents and related event flags are cleared. The

SYS_MODE[BUF_

GATE_ERR

] and SYS_MODE[BUF_GATE_CNT[4:0]] fields are also cleared.

The BUF_FLUSH bit is self-cleared within one internal clock cycle, and as such is not observable in a

logic high state through the I2C or SPI interfaces.

WAKE_SRC_BUF

Buffer WAKE-to-SLEEP transition source enable:

0: (BUF_WMRK | BUF_OVF) event flag condition is ignored by the auto-WAKE/SLEEP function

(default).

1: (BUF_WMRK | BUF_OVF) event flag condition is used by the auto-WAKE/SLEEP function.

FXLS8971CF enters SLEEP mode if the host system does not clear any of these flags before the

auto-sleep timer expires (the

ASLP_COUNT register sets the period). If the host clears the BUF_

WMRK and BUF_OVF flags by flushing or reading out the buffered data (one or more samples), the

auto-sleep timer resets and FXLS8971CF remains in the WAKE mode, regardless of the setting made

INT_EN[BUF_EN].

Note: The WAKE_SRC_BUF setting is only relevant when BUF_CONFIG1[BUF_MODE] = 01b

(Stream mode) or 10b (Stop mode).

Table 81. BUF_CONFIG2 register (address 27h) bit description

FXLS8971CF

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.1 — 7 March 2024

62 / 100

FXLS8971CF датащи(PDF) 62 Page - NXP Semiconductors

FXLS8971CF датащи(HTML) 62 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

датащи скачать

ссылки URL