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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8580 датащи(PDF) 24 Page - Wolfson Microelectronics plc |
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WM8580 датащи(HTML) 24 Page - Wolfson Microelectronics plc |
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24 / 97 page  WM8580 Production Data w PD Rev 4.3 August 2007 24 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R9 PAIF 1 09h 4:3 PAIFRX_BCLKSEL [1:0] 00 R10 PAIF 2 0Ah 4:3 PAIFTX_BCLKSEL [1:0] 00 R11 SAIF 1 0Bh 4:3 SAIF_BCLKSEL [1:0] 00 Master Mode BCLK Rate: 00 = 64 BCLKs per LRCLK 01 = 32 BCLKs per LRCLK 10 = 16 BCLKs per LRCLK 11 = BCLK = System Clock. Table 15 Master Mode BCLK Control AUDIO DATA FORMATS Five popular interface formats are supported: • Left Justified mode • Right Justified mode • I2S mode • DSP Mode A • DSP Mode B All five formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. Audio Data for each stereo channel is time multiplexed with the interface’s Left-Right-Clock (LRCLK), indicating whether the left or right channel is present. The LRCLK is also used as a timing reference to indicate the beginning or end of the data words. In Left Justified, Right Justified and I2S modes, the minimum number of BCLKs per LRCLK period is 2 times the selected word length. LRCLK must be high for a minimum of BCLK periods equivalent to the audio word length, and low for minimum of the same number of BCLK periods. Any mark to space ratio on LRCLK is acceptable provided these requirements are met. |
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