WM8580 datasheet(38/97 Pages) WOLFSON

38 / 97 page

WM8580

Production Data

PD Rev 4.3 August 2007

Figure 23 shows the application and release of MUTE whilst a full amplitude sinusoid is being played

at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to

decay exponentially from the DC level of the last input sample. The output will decay towards VMID

with a time constant of approximately 64 input samples. If MUTE is applied to all channels for 1024

or more input samples the DAC will be muted if IZD is set. When MUTE is de-asserted, the output

will restart immediately from the current input sample.

All other means of muting the DAC channels will cause a much more abrupt muting of the output.

This abrupt muting is referred to as an analog mute and it will switch the analog outputs immediately

to VMID.

DE-EMPHASIS MODE

A digital de-emphasis filter may be applied to each DAC channel. The de-emphasis filter for each

stereo channel is enabled under the control of DEEMP[2:0]. DEEMP[0] enables the de-emphasis

filter for DAC 1, DEEMP[1] enables the de-emphasis filter for DAC 2, and DEEMP[2] enables the de-

emphasis filter for DAC 3.

BIT

LABEL

DEFAULT

DESCRIPTION

2:0

DEEMP[2:0]

000

De-emphasis mode select:

DEEMP[0] = 1, enable De-

emphasis on DAC1.

DEEMP[1] = 1, enable De-

emphasis on DAC2.

DEEMP[2] = 1, enable De-

emphasis on DAC3.

R17

DAC Control 3

11h

DEEMPALL

0 = De-emphasis controlled by

DEEMP[2:0]

1 = De-emphasis enabled on all

DACs

Table 27 De-emphasis Register

Refer to Figure 41, Figure 42, Figure 43 and Figure 44 for details of the De-Emphasis modes at

different sample rates.

DAC OUTPUT PHASE

The DAC Phase control word determines whether the output of each DAC is non-inverted or inverted

BIT

LABEL

DEFAULT

DESCRIPTION

R18

DAC Control 4

12h

5:0

PHASE

[5:0]

111111

Controls phase of DAC outputs

0 = inverted

1 = non-inverted

PHASE[0] = 0 inverts phase of

DAC1L output

PHASE[1] = 0 inverts phase of

DAC1R output

PHASE[2] = 0 inverts phase of

DAC2L output

PHASE[3] = 0 inverts phase of

DAC2R output

PHASE[4] = 0 inverts phase of

DAC3L output

PHASE[5] = 0 inverts phase of

DAC3R output

Table 28 DAC Output Phase Register

WM8580 датащи(PDF) 38 Page - Wolfson Microelectronics plc

WM8580 датащи(HTML) 38 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

датащи скачать

ссылки URL