WM8580 datasheet(44/97 Pages) WOLFSON

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WM8580

Production Data

PD Rev 4.3 August 2007

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

CLKSEL

08h

3:2

ADC_CLKSEL

ADC clock source

00 = ADCMCLK pin

01 = PLLACLK

10 = PLLBCLK

11 = MCLK pin

R29

ADC

Control 1

1Dh

7:5

ADCRATE[2:0]

010

ADC Rate Control (only used when

the S/PDIF Transmitter is the only

interface sourcing the ADC)

000 = 128fs

001 = 192fs

010 = 256fs

011 = 384fs

100 = 512fs

101 = 768fs

110 = 1152fs

Table 34 ADC Clock Control

S/PDIF INTERFACES

The TX_CLKSEL register selects the clock for the S/PDIF Transmitter from ADCMCLK, PLLACLK,

PLLBCLK, or MCLK. The S/PDIF Receiver only uses PLLACLK, but both PLLACLK and PLLBCLK

are unavailable in user mode when the S/PDIF receiver is active. If the digital routing has been

configured such that the S/PDIF Transmitter is sourcing the S/PDIF Receiver, then PLLACLK is

automatically selected.

The rate at which the S/PDIF Transmitter operates at is determined by the S/PDIF Transmitter Rate

module. It calculates the rate based on the digital routing setup. When sourcing from the S/PDIF

Receiver (default), the SFRM_CLK is used in the rate calculation. When sourcing from the PAIF

Receiver, PAIFRX_LRCLK is used in the rate calculation. When sourcing from the SAIF Receiver,

SAIFRX_LRCLK is used in the rate calculation. When sourcing the ADC, the rate is determined by

either the PAIFTX_LRCLK (if the PAIF Transmitter also sources the ADC) or the ADC_RATE

Figure 28 S/PDIF Clock Selection

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