STE2004S datasheet(50/79 Pages) STMICROELECTRONICS

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Instruction set

STE2004S

50/79

5.1

Reset (RES)

At power-on, all internal registers are configured with the default value. The RAM content is

not defined. A reset pulse on the RES pad (active low) re-initializes the internal registers

content see

Table 10. All on-going communication with the host controller is interrupted if a

reset pulse is applied. After the power-on, the software reset instruction can be used to re-

load the reset configuration into the internal registers.

The default configuration is:

A memory blank instruction can be used to clear the DDRAM content.

Table 21. Partial display configuration

PD2

PD1

PD0

Section 1

Section 2

Reset state

8 + Icon row

0 + Icon row

8 + Icon row

16 + Icon row

000

0 + Icon row

16 + Icon row

8 + Icon row

16 + Icon row

Table 22. N-Line inversion

NW3

NW2

NW1

NW0

Description

Reset state

000

0-Line inversion

(Frame inversion)

2-Line inversion

3-Line inversion

4-Line inversion

0000

:::

15-Line inversion

16-Line inversion

– Horizontal addressing (V = 0)

– Multiplexing ratio (M[1:0]=0 - MUX 65)

– Normal instruction set (H[1:0] = 0)

– Frame rate (FR[1:0]=”75Hz”)

– Normal display (MX = MY = 0)

– Power down (PD = 1)

– Display blank (E = D = 0)

– Dual partial display disabled (PE=0)

– Address counter X[6: 0] = 0 and Y[4: 0] = 0

– VOP=0

– Temperature coefficient (TC[1: 0] = 0)

– Y-CARRIAGE=8

– Bias system (BS[2: 0] = 0)

– X-CARRIAGE=101

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