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STE2004S датащи(PDF) 68 Page - STMicroelectronics |
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STE2004S датащи(HTML) 68 Page - STMicroelectronics |
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68 / 79 page ![]() Electrical characteristics STE2004S 68/79 Tr;DA Rise time of SCLH signal Cb = 100pF(5) (6) 10 ns Tf;DA Fall time of SDAH signal Cb = 100pF(5) (6) 10 80 ns Tr;DA Rise time of SDAH signal Cb = 400pF(5) (6) 20 ns Tf;DA Fall time of SDAH signal Cb = 400pF(5) (6) 20 160 ns TSU;STO Setup time for STOP condition Cb = 100pF(5) (6) 160 ns Cb Capacitive load for SDAH and SCLH 100 400 pF Cb Capacitive load for SDAH +SDA line and SCLH +SCL line 400 pF Parallel interface ( Figure 73, Figure 74) TCYC System cycle time VDD1 = 1.7V; read and write 125 ns TCLW Control low pulse width (WR) 20 ns TCHW Control high pulse width (WR) 75 ns TCLR Control low pulse width (RD) 40 ns TCHR Control high pulse width (RD) 55 ns TEWHW Enable high pulse width (Write) 60 ns TEWLW Enable low pulse width (Write) 60 ns TEWHR Enable high pulse width (Read) 60 ns TEWLR Enable low pulse width (Read) 60 ns TSU(A) Address set-up time 10 ns TH(A) Address hold time 10 ns TSU1 Data set-up time 30 ns TH1 Data hold time 30 ns TSU2 Read access time 40 ns TH2 Output disable time 0 30 ns Table 28. AC operation Symbol Parameter Test condition Min. Typ. Max. Unit |
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