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STE2004S датащи(PDF) 69 Page - STMicroelectronics

номер детали STE2004S
подробное описание детали  102 x 65 single-chip LCD controller/driver
PDF  79 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STE2004S датащи(HTML) 69 Page - STMicroelectronics

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STE2004S
Electrical characteristics
69/79
Serial interface (
Figure 75)
FSCLK
Clock frequency
VDD1 = 1.7V;
8
MHz
TCYC
Clock cycle SCLK
125
ns
TPWH1
SCLK pulse width HIGH
60
ns
TPWL1
SCLK pulse width LOW
60
ns
TS2
CS setup time
VDD1 = 1.7V
40
ns
TH2
CS hold time
VDD1 = 1.7V
50
ns
TPWH2
CS minimum high time
VDD1 = 1.7V
50
ns
TS3
SD/C setup time
30
ns
TH3
SD/C hold time
30
ns
TS4
SDIN setup time
30
ns
TH4
SDIN hold time
40
ns
TS5
SDOUT access time
30
ns
TH5
SDOUT disable time vs.
SCLK
020
ns
TH6
SDOUT disable time vs.
CS
020
ns
1.
2.
For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
3.
Trise and Tfall (30%-70%) -10ns
4.
CVLCD is the filtering capacitor on VLCD
5.
All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and
VIH with an input voltage swing of VSS to VDD
6.
Cb is the capacitive load for each bus line.
Table 28. AC operation
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
F
frame
f
osc
960
----------
=



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