HT46R321

Rev. 1.00

19

August 3, 2007

Important Note for A/D initialisation:

Special care must be taken to initialise the A/D converter each time the Port B A/D channel selection bits are modified,

otherwise the EOCB flag may be in an undefined condition. An A/D initialisation is implemented by setting the START

bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selection bits being modified. Note

that if the Port B channel selection bits are all cleared to zero then an A/D initialisation is not required.

Register

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

ADRL

D3

D2

D1

D0

¾¾¾¾

ADRH

D11

D10

D9

D8

D7

D6

D5

D4

Note:

D0~D11 is A/D conversion result data bit LSB~MSB.

ADRL (20H), ADRH (21H) Register

Bit No.

Label

Function

0

1

2

ACS0

ACS1

ACS2

ACS3[ACSR], ACS2, ACS1, ACS0: selected A/D channel

3

4

5

PCR0

PCR1

PCR2

Port B, C configuration selection.

If PCR0, PCR1, PCR2 and PCR3[ACSR] are all zero,

the ADC circuit is power off to reduce power consumption

6

EOCB

Indicates end of A/D conversion. (0 = end of A/D conversion)

Each time bits 3~5 change state the A/D should be initialised by issuing a START signal, other-

wise the EOCB flag may have an undefined condition. See

²Important note for A/D initialisation².

7

START Starts the A/D conversion. (0

®1®0= start; 0®1= Reset A/D converter and set EOCB to ²1²)

ADCR (22H) Register

ACS2, ACS1, ACS0

Channel

000

AN0

001

AN1

010

AN2

011

AN3

100

AN4

101

AN5

11x

Undefined, can

¢t be used

A/D Channel

Bit No.

Label

Function

0

1

ADCS0

ADCS1

Select the A/D converter clock source.

2~6

¾

Unused bit, read as

²0².

7

TEST

For internal test only.

ACSR (23H) Register