HT46R321 datasheet(17/45 Pages) HOLTEK

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HT46R321

Rev. 1.00

August 3, 2007

control register, CMOS output or Schmitt trigger input

with or without pull-high resistor structures can be re-

configured dynamically (i.e. on-the-fly) under software

control. To function as an input, the corresponding latch

of the control register must write

²1². The input source

also depends on the control register. If the control regis-

ter bit is

²1², the input will read the pad state. If the con-

trol register bit is

²0², the contents of the latches will

move to the internal bus. The latter is possible in the

²read-modify-write² instruction.

After a device reset, the input/output lines will default to

inputs and remain at a high level or floating state, de-

pendent upon the pull-high configuration options. Each

bit of these input/output latches can be set or cleared by

the

²SET [m].i² and ²CLR [m].i² (m=12H, 14H or 18H) in-

structions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device.

Each I/O line has a pull-high option. Once the pull-high

configuration option is selected, the I/O line has a

pull-high resistor, otherwise, there

¢s none. Take note

that a non-pull-high I/O line operating in input mode will

cause a floating state.

Pin PA3 is pin-shared with the PFD signal. If the PFD

configuration option is selected, the output signal in the

output mode for PA3 will be the PFD signal generated by

the timer/event counter overflow signal. The input mode

always retains its original functions. Once the PFD op-

tion is selected, the PFD output signal is controlled by

the PA3 data register only. Writing a

²1² to the PA3 data

²0² will force the PA3 to remain at ²0². The I/O functions

for PA3 are shown below.

I/O

Mode

I/P

(Normal)

O/P

(Normal)

I/P

(PFD)

O/P

(PFD)

PA3

Logical

Input

Logical

Output

Logical

Input

PFD

(Timer on)

Note:

The PFD frequency is the timer/event counter

overflow frequency divided by 2.

Pins PD6 and PD5 are pin-shared with INT, TMR pins

respectively.

The PB can also be used as A/D converter inputs. The

A/D function will be described later. There are two PWM

functions shared with pins PD0 and PD1. If the PWM

functions are enabled, the PWM signals will appear on

PD0 and PD1, the pins are setup as outputs. Writing a

²1² to the PD0 or PD1 data register will enable the PWM

outputs to function while writing a

²0² will force the PD0

and PD1 outputs to remain at

²0². The I/O functions of

PD0 and PD1 are as shown.

I/O

Mode

I/P

(Normal)

O/P

(Normal)

I/P

(PWM)

O/P

(PWM)

PD0

PD1

Logical

Input

Logical

Output

Logical

Input

PWM0

PWM1

It is recommended that unused I/O lines should be setup

as output pins by software instructions to avoid consum-

ing power under input floating states.

PWM

The microcontroller provides a 2 channel (6+2) bits

PWM0/PWM1 output shared with PD0/PD1. The PWM

channel has its data register denoted as PWM0 and

PWM1. The frequency source of the PWM counter co-

mes from fSYS. The PWM register is an eight bit register.

Once PD0/PD1 are selected as PWM outputs and the

output function of PD0/PD1 is enabled (PDC.0=

²0² or

f S Y S / 2

P W M

[ P W M ] = 1 0 0

[ P W M ] = 1 0 1

P W M

[ P W M ] = 1 0 2

P W M

[ P W M ] = 1 0 3

P W M

P W M c y c l e : 2 5 6 / f S Y S

2 5 / 6 4

2 6 / 6 4

2 5 / 6 4

2 6 / 6 4

2 5 / 6 4

2 6 / 6 4

2 5 / 6 4

2 6 / 6 4

M o d u l a t i o n c y c l e 0

P W M m o d u l a t i o n p e r i o d : 6 4 / f S Y S

M o d u l a t i o n c y c l e 1

M o d u l a t i o n c y c l e 2

M o d u l a t i o n c y c l e 3

M o d u l a t i o n c y c l e 0

6+2 PWM Mode

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