HT46R321 datasheet(18/45 Pages) HOLTEK

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HT46R321

Rev. 1.00

August 3, 2007

PDC.1=

²0²), writing a 1 to the PD0/PD1 data register

will enable the PWM output function while writing a

²0²

will force the PD0/PD1 outputs to stay at

²0².

A PWM cycle is divided into four modulation cycles

(modulation cycle 0~modulation cycle 3). Each modula-

tion cycle has 64 PWM input clock period. In a (6+2) bit

PWM function, the contents of the PWM register is di-

vided into two groups. Group 1 of the PWM register is

denoted by DC which is the value of PWM.7~PWM.2.

Group 2 is denoted by AC which is the value of

PWM.1~PWM.0.

In a PWM cycle, the duty cycle of each modulation cycle

is shown in the table.

Parameter

AC (0~3)

Duty Cycle

Modulation cycle i

(i=0~3)

i<AC

DC+1

³AC

The modulation frequency, cycle frequency and cycle

duty of the PWM output signal are summarized in the

following table.

PWM

Modulation

Frequency

PWM Cycle

Frequency

PWM Cycle

Duty

fSYS/64

fSYS/256

[PWM]/256

Peripheral Clock Output

- PCK

The device also provides a Peripheral Clock Output

(PCK) which is pin-shared with PD2. Once the PD2 is

selected as the PCK outputs and the output function of

PD2 is enabled (PDC.2 =

²0²), writing 1 to PD2 data reg-

ister will enable the PCK output function and writing

²0²

will force the PD2 to stay at

²0².

The PCK clock frequency can be optional : fSYS/16 or

fSYS/32 ( by configuration option).

PCK output = 500kHz or 250kHz if fSYS=8MHz.

Recommend to clear PD2 before entering HALT mode.

LED Driver

The device provides a maximum of 8

´4 LED drivers

which uses I/O Ports PA0~PA7 and PD1~PD4 with dou-

ble the usual sink/source current drive capabilities. To

use the LED driver function, PA0~PA7and PD1~PD4

must be setup as outputs.

A/D Converter

The 6 channel 12-bit resolution A/D converter is imple-

mented in the microcontrollers. The reference voltage

for the A/D is VDD. The A/D converter contains 4 special

registers, which are; ADRL, ADRH, ADCR and ACSR.

The ADRH and ADRL registers are the A/D conversion

result register higher-order byte and lower-order byte

and are read-only. After the A/D conversion has com-

pleted, the ADRL and ADRH registers should be read to

get the conversion result data. The ADCR register is an

A/D converter control register, which defines the A/D

channel number, analog channel select, start A/D con-

version control bit and the end of A/D conversion flag. It

is used to start an A/D conversion, define the PB config-

uration, select the converted analog channel, and give

the START bit a raising edge and a falling edge

®1®0). At the end of an A/D conversion, the EOCB

bit is cleared and an A/D converter interrupt occurs, if

the A/D converter interrupt is enabled. The ACSR

select the A/D clock source.

The A/D converter control register is used to control the

A/D converter. Bit2~bit0 of the ADCR register is used to

select an analog input channel. There are a total of 6

channels to select. Bit5~bit3 of the ADCR register is used

to set the PB configurations. PB can be configured as an

analog input or as a digital I/O line decided by these 3

bits. Once a PB line is selected as an analog input, the

I/O functions and pull-high resistor of this I/O line are dis-

abled, and the A/D converter circuit is powered on. The

EOCB bit, bit6 of ADCR, is the end of A/D conversion

flag. This bit is monitored to check when the A/D conver-

sion has completed. The START bit of the ADCR register

is used to initiate the A/D conversion process. When the

START bit is provided with a raising edge and then a fall-

ing edge, the A/D conversion process will begin. In order

to ensure that the A/D conversion is completed, the

START should remain at

²0² until the EOCB flag is

cleared to

²0² which indicates the end of the A/D conver-

sion.

Bit 7 of the ACSR register is used for test purposes only

and must not be used for other purposes by the applica-

tion program. Bit1 and bit0 of the ACSR register are

used to select the A/D clock source.

When the A/D conversion has completed, the A/D inter-

rupt request flag will be set. The EOCB bit is set to

²1²

when the START bit is set from

²0² to ²1².

P C K D i v i d e r

P D 2 / P C K

f S Y S / 4

P C K O p t i o n

P D 2

P C K D i v i d e r R a t i o O p t i o n

( ¸ 4 o r ¸ 8 )

P C K C l o c k

f P C K

P A 0 ~ P A 7

P D 1 ~ P D 4

H T - M C U

L E D D i s p l a y

8 x 4 A r r a y

LED Driver

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