HT46R321 datasheet(15/45 Pages) HOLTEK

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HT46R321

Rev. 1.00

August 3, 2007

Bit No.

Label

Function

TPSC0

TPSC1

TPSC2

Defines the prescaler stages, PSC2, PSC1, PSC0=

000: fINT=fSYS

001: fINT=fSYS/2

010: fINT=fSYS/4

011: fINT=fSYS/8

100: fINT=fSYS/16

101: fINT=fSYS/32

110: fINT=fSYS/64

111: fINT=fSYS/128

3TE

Defines the TMR active edge of the timer/event counter:

In Event Counter Mode (TM1,TM0)=(0,1):

1:count on falling edge;

0:count on rising edge

In Pulse Width measurement mode (TM1,TM0)=(1,1):

1: start counting on the rising edge, stop on the falling edge;

0: start counting on the falling edge, stop on the rising edge

TON

Enable or disable the timer counting

(0=disable; 1=enable)

Unused bits, read as

²0²

TM0

TM1

Defines the operating mode (TM1, TM0)=

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

TMRC (0EH) Register

Timer/Event Counter

Two timer/event counter (TMR) are implemented in the

microcontroller. The timer/event counter contains an

8-bit programmable count-up counter and the clock may

come from external source or an internal clock source.

An internal clock source comes from fsys (fSYS/4). Using

an external clock input allows the user to count external

events, measure time internals or pulse widths, or gen-

erate an accurate time base. While using the internal

clock allows the user to generate an accurate time base.

There are two registers related to the Timer/Event

Counter; TMR, TMRC. Writing TMR will transfer the

specified data to Timer/Event Counter registers. Read-

ing the TMR will read the contents of the Timer/Event

Counter. The TMRC is a control register, which defines

the operating mode, counting enable or disable and an

active edge.

The TM0 & TM1 bits define the operation mode. The

event count mode is used to count external events,

which means that the clock source is from an external

TMR pin. The timer mode functions as a normal timer

with the clock source coming from the internal selected

clock source. Finally, the pulse width measurement

mode can be used to count the high or low-level duration

of the external signal TMR, and the counting is based on

the internal selected clock source.

In the event count or timer mode, the timer/event coun-

ter starts counting at the current contents in the

timer/event counter and ends at FFH. Once an overflow

occurs, the counter is reloaded from the timer/event

counter preload register, and generates an interrupt re-

quest flag TF. In the pulse width measurement mode

with the values of the TON & TE equal to 1, after the

TMR has received a transient from low to high (or high to

low if the TE bit is

²0²), it will start counting until the TMR

returns to the original level and resets the TON. The

measured result remains in the timer/event counter

even if the activated transient occurs again. In other

words, only 1-cycle measurement can be made until the

TON is set. The cycle measurement will re-function as

long as it receives further transient pulse. In this opera-

tion mode, the timer/event counter begins counting not

according to the logic level but to the transient edges. In

the case of counter overflow, the counter is reloaded

from the timer/event counter register and issues an in-

terrupt request, as in the other two modes, i.e., event

and timer modes.

To enable the counting operation, the Timer ON bit TON

should be set to 1. In the pulse width measurement

mode, the TON is automatically cleared after the mea-

surement cycle is completed. But in the other two

modes, the TON can only be reset by instructions. The

overflow of the Timer/Event Counter is one of the

wake-up sources and can also be applied to a PFD (Pro-

grammable Frequency Divider) output by options. When

the PFD function is selected, executing

²SET [PA].3² in-

struction to enable PFD output and executing

²CLR

[PA].3

² instruction to disable PFD output.

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