LT7184S datasheet(28/52 Pages) AD

28 / 52 page

Data Sheet

LT7184S

analog.com

Rev. 0

28 of 52

APPLICATIONS INFORMATION

Using Resistor Configuration Pins

The LT7184S has four resistor configuration pins, each using a single ±1% resistor to select key operating parameters.

The resistor configuration pins are ASEL, VOUT0_CFG, VOUT1_CFG, and PWM_CFG. The resistance from each of these pins to

GND is measured upon power-up and/or execution of a RESTORE_USER_ALL or MFR_RESET command. The function

of each resistor configuration pin is described in the following sections.

If bit 6 of the MFR_CONFIG_ALL_LT7184S command is set to 1 in EEPROM, the configuration resistors are ignored on

VOUT0_CFG, VOUT1_CFG, and PWM_CFG while the ASEL resistor is always respected. Refer to the MFR_ADDRESS command

in the LT7184S PMBus/I2C Reference Manual for information about setting the serial interface device address,

including ASEL configuration resistor selection.

Setting Output Voltage

The VOUT_COMMAND specifies the output voltage when the channel is enabled. VOUT_COMMAND can be initialized

using resistors on the VOUT0_CFG and VOUT1_CFG pins based on the values in Table 7. A resistor between VOUT0_CFG and GND

configures channel 0. If Channel 1 is configured as an independent output from Channel 0, then a resistor between

VOUT1_CFG and GND configures Channel 1. If PolyPhase configuration is selected (by connecting a 5.6kΩ ±10% resistor

between PWM_CFG and GND), then VOUT0_CFG configures both Channels 0 and 1, and VOUT1_CFG is repurposed to

configure the PolyPhase operation.

Table 7. VOUTN_CFG Pin Configuration Resistor Selection

RESISTOR VALUE

(±1%)1

OUTPUT VOLTAGE SET

POINT (V)2

VOUT RANGE MODE3

REGULATOR ENABLE4

Floating or VDD185

Initialized from NVM

(Default 0.5V)

Initialized from NVM

(Default full VOUT range)

Initialized from NVM

124kΩ

Full VOUT range, Supports

0.4V ≤ VOUT ≤ 5.5V

Regulator is enabled if RUN

is asserted high.

(OPERATION = 0x80,

ON_OFF_CONFIG initialized

from NVM, default requires

OPERATION = 0x80 and

RUN pin asserted)

107kΩ

3.3V

93.1kΩ

2.5V

80.6kΩ

1.8V

69.8kΩ

1.5V

60.4kΩ

1.35V

51.1kΩ

1.2V

High-performance low-VOUT

mode if set in NVM.

Offers enhanced accuracy

and transient response for

0.6V ≤ VOUT ≤ 1.375V

43.2kΩ

1.1V

36.5kΩ

1.0V

30.9kΩ

0.9V

25.5kΩ

0.85V

21kΩ

0.8V

16.5kΩ

0.75V

11.8kΩ

0.7V

6.65kΩ

0.6V

(GND)

Initialized from NVM

(default 0.5V)

Initialized from NVM

(default full VOUT range)

Regulator disabled and

RUN pin ignored.

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