LT7184S datasheet(15/52 Pages) AD

15 / 52 page

Data Sheet

LT7184S

analog.com

Rev. 0

15 of 52

Name

DESCRIPTION

pulls down the FAULT0 pin, the LT7184 channel 0 regulator turns off immediately. If

PolyPhase configuration is used, tie together the FAULTN pins of all PolyPhase

channels. If the PolyPhase configuration is used, or if the Fault pin reporting or sharing

is required, a pull-up resistor of 6.8kΩ or greater to 1.6V to 5.5V is required. FAULT0 pin

may be tied directly to DRVCC if the FAULT0 pin function is not required.

ALERT

Open-Drain Alert Output. If the ALERT pin function is used, a pull-up resistor of 1.6V to

5.5V is required. If the ALERT pin function is not used, the pin may be connected to the

ground.

SCL

Serial Bus Clock Input and Output. The LT7184S may hold SCL low if clock stretching is

enabled (PMBus speeds 400kHz - 1MHz only). A pull-up resistor of 1.6V to 5.5V is required

for PMBus/I2C operation. If serial bus operation is not required, SCL may be connected

to the ground.

SDA

Serial Bus Data Input and Output. A pull-up resistor of 1.6V to 5.5V is required for

PMBus/I2C operation. If serial bus operation is not required, the SDA may be connected

to the ground.

SYNC

External Clock Synchronization Input/Output. When driven with an external clock, an

internal phase-locked loop synchronizes the switching regulator output with the rising

edge of the external clock. If configured as an output (MFR_SYNC_CONFIG_LT7184 bit 0

is set to 1), the LT7184S drives the SYNC pin output at the switching clock frequency set

by the FREQUENCY_SWITCH command with a voltage swing of 0V to VDD18.

PWM_CFG

PWM Configuration Resistor Pin. Connect a 1% resistor from PWM_CFG to the ground

(SGND or PGND) according to Table 9 in the Applications Information section to select

frequency, phase, and mode configurations. The PWM_CFG pin is read at LT7184S start-

up. See Applications Information for more details.

PGOOD0

Power Good Indicator Output for channel 0. PGOOD0 is pulled low when the channel 0

regulator output is outside of the OV/UV fault thresholds when Channel 0 is disabled,

and during on/off sequencing. The PGOOD0 output is deglitched by an internal

configurable timer. If the PGOOD0 pin function is not used, it may be connected to

the ground.

VSENSE0P

Output voltage positive sense input. Connect to the Channel 0 output voltage sense

point.

VSENSE0N

Output voltage negative sense input. Connect to the Channel 0 output voltage sense

ground point.

PGOOD1

Power Good Indicator Output for Channel 1. PGOOD1 is pulled low when the Channel 0

regulator output is outside of the OV/UV fault thresholds when Channel 1 is disabled and

during on/off sequencing. The PGOOD1 output is deglitched by an internal configurable

timer. If the PGOOD1 pin function is not used, it may be connected to the ground.

34, 35,

Exposed

pad 37

SW0

Output of the Channel 0 internal power switches. Connect these pins together and

connect the Channel 0 inductor and BOOST0 capacitor. This node should be sized to

support the maximum load current for Channel 0 and be spaced away from all other PCB

metal.

BOOST0

Boosted floating driver supply for Channel 0. Connect a 0.1µF boost capacitor from

BOOST0 to SW0 as close as possible to the LT7184S using only the top PCB layer. The

normal operation voltage swing on this pin is from DRVCC to PVIN0 + DRVCC.

LT7184S датащи(PDF) 15 Page - Analog Devices

LT7184S датащи(HTML) 15 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

датащи скачать

ссылки URL