LT7184S datasheet(13/52 Pages) AD

13 / 52 page

Data Sheet

LT7184S

analog.com

Rev. 0

13 of 52

Name

DESCRIPTION

ITH0

Error amplifier output and switching regulator compensation for Channel 0. Connect the

appropriate external components between ITH0 and SGND to compensate the regulator

loop frequency response for Channel 0 or connect to INTVCC to select internal

compensation for Channel 0.

ITH1

Error amplifier output and switching regulator compensation for channel 1. Connect the

appropriate external components between ITH1 and SGND to compensate the regulator

loop frequency response for Channel 1, or connect to INTVCC to select internal

compensation for Channel 1.

INTVCC

Internal 3V LDO regulator bypass. This LDO regulator output provides a supply current

for internal circuitry. This pin must be bypassed to SGND with a 10µF or greater, low ESR

ceramic capacitor as close as possible to the IC on the top Printed Circuit Board (PCB)

layer. Do not load the INTVCC pin with external circuitry.

VDD18

Internal 1.8V regulator bypass. This pin must be bypassed to SGND with a 4.7µF or

greater low ESR ceramic capacitor as close as possible to the LT7184S on the top PCB

layer. Do not load the VDD18 pin with external circuitry.

VOUT0_CFG

Output voltage configuration for channel 0. Connect a 1% resistor from VOUT0_CFG to GND

(SGND or PGND) according to Table 7 in the Applications Information section to select

one of sixteen output voltage set points. If left floating or connected to VDD18, the LT7184S

uses the value of VOUT_COMMAND programmed in EEPROM to set the output voltage

set point. The VOUT0_CFG pin is only read at the start-up.

DRVCC

Internal 3.5V LDO regulator bypass. The DRVCC regulator provides the supply current for

the power FET drivers. This pin must be bypassed to PGND with a 100nF or greater low

Equivalent series resistance (ESR) ceramic capacitor as close as possible to the LT7184S

using the top PCB layer, and a bulk 10µF low ESR ceramic capacitor. Do not load the

DRVCC pin with external circuitry with the optional exceptions of the pull-up resistor for

the SHARE_CLK pin and/or the RUN0, RUN1, FAULT0, or FAULT1 pins.

Exposed

pads 38,

PGND

Power ground. The (-) terminal of the PVIN1 input bypass capacitors and the (-) terminal

of the output capacitors (COUT0 and COUT1) should be connected to these pins with low-

impedance connections. The PCB must be designed to provide low electrical and

thermal impedance to PGND.

PVIN1

Power supply input for Channel 1. This pin must be bypassed to PGND as close as

possible to the LT7184S with a low ESR capacitor of value 4.7µF or more using the top

PCB layer.

BOOST1

Boosted floating driver supply for Channel 1. Connect a 0.1µF boost capacitor from

BOOST1 to SW1 as close as possible to the LT7184S using only the top PCB layer. The

normal operation voltage swing on this pin is from DRVCC to PVIN1 + DRVCC.

12, 13,

Exposed

pad 40

SW1

The output of the Channel 1 internal power switches. Connect these pins together and

connect the Channel 1 inductor and BOOST1 capacitor. This node should be sized to

support the maximum load current for Channel 1 and be spaced away from all other PCB

metal.

ASEL

Serial bus address configuration pin. Connect a 1% resistor from ASEL to ground (SGND

or PGND) to select one of sixteen serial bus interface addresses. The ASEL pin is read at

start-up. If the ASEL pin is left floating, the factory default 7-Bit device address is 0x4F. If

the ASEL pin is grounded, the factory default device address is 0x40.

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