LT7184S datasheet(31/52 Pages) AD

31 / 52 page

Data Sheet

LT7184S

analog.com

Rev. 0

31 of 52

The SYNC pin is a clock output when the MFR_SYNC_CONFIG_LT7184S Bit 0 is set to 1.

The NVM default for MFR_PWM_MODE_LT7184S bits [13:11] is 0b001, which corresponds to gMEA = 1250μs for high-

performance low-VOUT mode and gMEA = 310μs for standard mode, regardless of internal or external compensation.

The PWM_CFG resistor selection is performed with a table lookup function within the device on power-up. Use

only 1% resistors for the PWM_CFG resistor selection as shown in Table 9, or program the devices using the PMBus

commands and NVM.

PolyPhase Load Sharing

Multiple LT7184S channels can be connected in parallel to provide a balanced PolyPhase load-share solution. The

analog current mode control architecture of the LT7184S ensures that load-sharing remains balanced among the

PolyPhase channels.

The corresponding ITHN, FAULTN, PVIN, VSENSENP, and VSENSENN pins must be connected among all PolyPhase channels,

and the SYNC and SHARE_CLK pins must be connected among all PolyPhase devices. The PWM switching phases

should be separated by 360°/n degrees, where n is the number of phases in the PolyPhase array. In PolyPhase, exactly

one device, either an LT7184S or an external clock source, must be configured to drive a clock on the common SYNC

node.

In a PolyPhase array, exactly one LT7184S channel must be configured as a leader (MFR_CHAN_CONFIG_LT7184S

Bit 8 set to 0), and all other PolyPhase channels must be configured as followers (Bit 8 set to 1).

The PolyPhase mode can be selected by connecting a 5.6kΩ ±10% resistor from PWM_CFG to GND if

MFR_CONFIG_ALL_LT7184S Bit 6 is not set to ignore CFG pins. Resistor configuration options are available to support

2, 3, 4, or 6-phase PolyPhase solutions. When a 5.6kΩ resistor is connected on PWM_CFG, VOUT_COMMAND for

Channel 1 is set to the same value as Channel 0 based on the VOUT0_CFG resistor, and the VOUT1_CFG resistor selects the

PolyPhase configuration as shown in Table 10. For 2, 4, or 6-phase operation, the PWM_CFG pins of up to three

LT7184S devices may be connected to a single 5.6k resistor. Figure 34 illustrates two LT7184S devices configured for

4-phase operation. Separate PWM_CFG configuration resistors are required, as shown in Typical Applications, for

PolyPhase arrays with 8 phases. PMBus programming is required for at least some of the devices in arrays with more

than 6 phases: to set PolyPhase follower mode (MFR_CHAN_CONFIG_LT7184S Bit 8) and select the appropriate phase

(MFR_PWM_PHASE_LT7814S) for every Channel in a large PolyPhase array.

Figure 34.4-Phase PolyPhase 1.2V/36A Regulator

BOOST0

LT7184S

PWM_CFG

VOUT1_CFG

PHASE 0° AND 180°

PVIN0

PVIN1

SHARE_CLK

FAULT0

ITH0

FAULT1

ITH1

VSENSE0P

VSENSE1P

VSENSE0N

VSENSE1N

VOUT0_CFG

1.2kΩ

80.6kΩ

5.6kΩ

SW1

SW0

(SELECTS

POLYPHASE)

(SELECTS

1MHz,

0° TO 180°,

LEADER/FOLLOWER,

SYNC OUTPUT)

LT7184S

PWM_CFG

VOUT1_CFG

PHASE 90° AND 270°

PVIN0

PVIN1

SHARE_CLK

FAULT0

ITH0

FAULT1

ITH1

VSENSE0P

VSENSE1P

VSENSE0N

VSENSE1N

VOUT0_CFG

SW1

SW0

51.1kΩ

60.4kΩ

(SELECTS

VOUT = 1.2V)

(SELECTS

1MHz,

90° TO 270°

FOLLOWER/FOLLOWER,

SYNC INPUT)

6.8kΩ

51.1kΩ

PVIN

4.5V TO 15V

VOUT

(1.2V, 36A)

6.8kΩ

4.7nF

RUN0

RUN1

SYNC (OUTPUT)

SYNC (INPUT)

SGND

2.4mF

DRVCC

INTVCC

BOOST1

BOOST0

10µF

RUN0

RUN1

DRVCC

VDD18

4.7µF

VDD18

4.7µF

100nF

330nH

10µF

ASEL

PGOOD0

PGOOD1

PGOOD0

PGOOD1

10µF

(SELECTS

VOUT = 1.2V)

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