PM7367 datasheet(107/323 Pages) PMC

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PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

implemented. However, when all four byte enables are negated, no access is

made to this register.

RLGA[0]:

The receive link group #0 active bit (RLGA[0]) monitors for transitions on the

RD[3:0] and RCLK[3:0] inputs. RLGA[0] is set high when each of RD[3:0]

has been sampled low and sampled high by rising edges of the

corresponding RCLK[3:0] inputs, and is set low when this register is read.

RLGA[1]:

The receive link group #1 active bit (RLGA[1]) monitors for transitions on the

RD[7:4] and RCLK[7:4] inputs. RLGA[1] is set high when each of RD[7:4]

has been sampled low and sampled high by rising edges of the

corresponding RCLK[7:4] inputs, and is set low when this register is read.

RLGA[2]:

The receive link group #2 active bit (RLGA[2]) monitors for transitions on the

RD[11:8] and RCLK[11:8] inputs. RLGA[2] is set high when each of RD[11:8]

has been sampled low and sampled high by rising edges of the

corresponding RCLK[11:8] inputs, and is set low when this register is read.

RLGA[3]:

The receive link group #3 active bit (RLGA[3]) monitors for transitions on the

RD[15:12] and RCLK[15:12] inputs. RLGA[3] is set high when each of

RD[15:12] has been sampled low and sampled high by rising edges of the

corresponding RCLK[15:12] inputs, and is set low when this register is read.

RLGA[4]:

The receive link group #4 active bit (RLGA[4]) monitors for transitions on the

RD[19:16] and RCLK[19:16] inputs. RLGA[4] is set high when each of

RD[19:16] has been sampled low and sampled high by rising edges of the

corresponding RCLK[19:16] inputs, and is set low when this register is read.

RLGA[5]:

The receive link group #5 active bit (RLGA[5]) monitors for transitions on the

RD[23:20] and RCLK[23:20] inputs. RLGA[5] is set high when each of

RD[23:20] has been sampled low and sampled high by rising edges of the

corresponding RCLK[23:20] inputs, and is set low when this register is read.

RLGA[6]:

The receive link group #6 active bit (RLGA[6]) monitors for transitions on the

RD[27:24] and RCLK[27:24] inputs. RLGA[6] is set high when each of

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