MPC9447

TIMING SOLUTIONS

7

MOTOROLA

The pin--to--pin skew is defined as the worst case difference in

propagation delay between any similar delay path within a

single device

The time from the output controlled edge to the non--controlled

edge, divided by the time between output controlled edges,

expressed as a percentage

GND

GND

GND

GND

GND

CCLK

2.4

1.8V

0.55

0.6V

Figure 11. Output Duty Cycle (DC)

Figure 12. Output Transition Time Test Reference

The variation in cycle time of a signal between adjacent cycles,

over a random sample of adjacent cycle pairs

Figure 13. Cycle--to--Cycle Jitter

GND

GND

CCLK

GND

GND

CCLK

PCLK

CLK_STOP

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MPC9447

3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer

NETCOM

IDT™ 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MPC9447

7