MPC9447

TIMING SOLUTIONS

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MOTOROLA

APPLICATION INFORMATION

Figure 3. Output Clock Stop (CLK_STOP) Timing

Diagram

CCLK0 or

CCLK1

CLK_STOP

Q0 to Q8

Driving Transmission Lines

The MPC9447 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user, the output

drivers were designed to exhibit the lowest impedance

outputs can drive either parallel or series terminated

transmission lines. For more information on transmission

lines, the reader is referred to Motorola application note

AN1091.

In most high performance clock networks,

point--to--point distribution of signals is the method of choice.

In a point--to--point scheme, either series terminated or

parallel terminated transmission lines can be used. The

parallel technique terminates the signal at the end of the line

Figure 4. Single versus Dual Transmission Lines

17Ω

IN

MPC9447

OUTPUT

BUFFER

OutA

17Ω

IN

MPC9447

OUTPUT

BUFFER

OutB0

OutB1

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each

output of the MPC9447 clock driver.

For the series

terminated case, however, there is no DC current draw; thus,

the outputs can drive multiple series terminated lines.

Figure 4 “Single versus Dual Transmission Lines” illustrates

an output driving a single series terminated line versus two

series terminated lines in parallel. When taken to its extreme,

the fanout of the MPC9447 clock driver is effectively doubled

Figure 5. Single versus Dual Line Termination

Waveforms

TIME (nS)

3.0

2.5

2.0

1.5

1.0

0.5

0

2

4

6

8

101214

OutB

OutA

In

The waveform plots in Figure 5 “Single versus Dual Line

Termination Waveforms” show the simulation results of an

output driving a single line versus two lines. In both cases,

the drive capability of the MPC9447 output buffer is more

than sufficient to drive 50Ω transmission lines on the incident

edge. Note from the delay measurements in the simulations

a delta of only 43ps exists between the two differently loaded

outputs. This suggests that the dual line driving need not be

used exclusively to maintain the tight output--to--output skew

of the MPC9447. The output waveform in Figure 5 “Single

versus Dual Line Termination Waveforms” shows a step in

the waveform; this step is caused by the impedance

mismatch seen looking into the driver. The parallel

combination of the 33Ω series resistor plus the output

impedance does not match the parallel combination of the

line impedances. The voltage wave launched down the two

lines will equal:

= 1.28V

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.5V. It will then increment

towards the quiescent 3.0V in steps separated by one round

trip delay (in this case 4.0ns).

Since this step is well above the threshold region it will not

cause any false clock triggering; however, designers may be

uncomfortable with unwanted reflections on the line. To

better match the impedances when driving multiple lines, the

situation in Figure 6 “Optimized Dual Line Termination”

should be used. In this case, the series terminating resistors

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MPC9447

3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer

NETCOM

IDT™ 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MPC9447

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