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MPC9447 датащи(PDF) 4 Page - Integrated Device Technology |
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MPC9447 датащи(HTML) 4 Page - Integrated Device Technology |
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4 / 9 page ![]() MPC9447 MOTOROLA TIMING SOLUTIONS 4 Table 7. DC Characteristics (VCC =2.5V ± 5%, TA =--40°Cto+85°C) Symbol Characteristics Min Typ Max Unit Condition VIH Input High Voltage 1.7 VCC +0.3 V LVCMOS VIL Input Low Voltage -0.3 0.7 V LVCMOS VOH Output High Voltage 1.8 V IOH =-15 mAa VOL Output Low Voltage 0.6 V IOL =15mA ZOUT Output Impedance 19 Ω IIN Input Currentb ±300 µA VIN =VCC or GND ICCQ Maximum Quiescent Supply Currentc 2.0 mA All VCC Pins a. The MPC9447 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives one 50Ω series terminated transmission lines per output (VCC=2.5V). b. Inputs have pull-down or pull-up resistors affecting the input current. c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 8. AC Characteristics (VCC =2.5V ± 5%, TA = --40°Cto+85°C)a Symbol Characteristics Min Typ Max Unit Condition fref Input Frequency 0 350 MHz fmax Output frequency 0 350 MHz fP,REF Reference Input Pulse Width 1.4 ns tr,tf CCLK0, CCLK1 Input Rise/Fall Time 1.0b ns 0.7to1.7V tPLH/HL Propagation Delay CCLK0 or CCLK1 to any Q 1.7 4.4 ns tPLZ, HZ Output Disable Time 11 ns tPZL, ZH Output Enable Time 11 ns tS Setup Time CCLK0 or CCLK1 to CLK_STOPc 0.0 ns tH Hold Time CCLK0 or CCLK1 to CLK_STOPc 1.0 ns tsk(O) Output-to-Output Skew 150 ps tsk(PP) Device-to-Device Skew 2.7 ns tSK(P) DCQ Ouput Pulse Skewd Output Duty Cycle fQ<350 MHz 45 50 200 55 ps % DCREF = 50% tr,tf Output Rise/Fall Time 0.1 1.0 ns 0.6to1.8V tJIT(CC) Cycle-to-cycle jitter RMS (1 σ) TBD ps a. AC characteristics apply for parallel output termination of 50Ω to VTT. b. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. c. Setup and hold times are referenced to the falling edge of the selected clock signal input. d. Output pulse skew is the absolute difference of the propagation delay times: | tPLH -tPHL |. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com MPC9447 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer NETCOM IDT™ 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MPC9447 4 |
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