CS42428 datasheet(23/73 Pages) CIRRUS

23 / 73 page

DS605F1

CS42428

4.4

Clock Generation

The clock generation for the CS42428 is shown in the figure below. The internal MCLK is derived from the

output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the

SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of PLL

lock to the other source input.

4.4.1

PLL and Jitter Attenuation

The PLL can be configured to lock onto the incoming ADC_LRCK signal from the ADC Serial Port and

generate the required internal master clock frequency. There are some applications where low jitter in the

recovered clock, presented on the RMCK pin, is important. For this reason, the PLL has been designed

to have good jitter-attenuation characteristics. By setting the PLL_LRCK bit to a ‘1’ in the register “Clock

Control (address 06h)” on page 48, the PLL will lock to the incoming ADC_LRCK and generate an output

master clock (RMCK) of 256Fs. Table 2 shows the output of the PLL with typical input Fs values for

ADC_LRCK.

See “Appendix B: PLL Filter” on page 62 for more information concerning PLL operation, required filter

components, optimal layout guidelines, and jitter-attenuation characteristics.

ADC_LRCK

(slave mode)

PLL (256Fs)

8.192 -

49.152 M Hz

PLL_LRCK bit

SW _CTRLx bits

(manual or auto

switch)

OMCK

Auto Detect

Input Clock

1,1.5, 2, 4

single

speed

256

double

speed

128

quad

speed

single

speed

double

speed

quad

speed

not O LM

OLM #1

DAC_FMx bits

ADC_FMx bits

DAC_OLx

or ADC_O Lx bits

ADC_OLx and

ADC_SP SELx bits

ADC_SCLK

DAC_SCLK

DAC_LRCK

ADC_LRCK

RMCK

OLM #2

not O LM

OLM #1

OLM #2

128FS

256FS

128FS

256FS

Internal

MCLK

RMCK_DIVx bits

Figure 10. Clock Generation

CS42428 датащи(PDF) 23 Page - Cirrus Logic

CS42428 датащи(HTML) 23 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

датащи скачать

ссылки URL