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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PACE1757M датащи(PDF) 31 Page - Pyramid Semiconductor Corporation |
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PACE1757M датащи(HTML) 31 Page - Pyramid Semiconductor Corporation |
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31 / 34 page  PACE 1757 M/ME Page 31 of 34 Document # MICRO-10 REV B PIC REGISTER MAP DEFINITIONS CONTROL REGISTER (Default = 0000) PR1 Enable Parity Checking/Generation for Memory Addresses 0000-3FFF. PR2 Enable Parity Checking/Generation for Memory Addresses 4000-7FFF. PR3 Enable Parity Checking/Generation for Memory Addresses 8000-BFFF. PR4 Enable Parity Checking/Generation for Memory Addresses C000-FFFF. ODD Enable ODD Parity. EST Enable Three State Control on PIC Generated Strobes: IOR, IOW, MEMR, MEMW. EAD Enable Three State Control on PIC Generated Address: A0-A15. EXR Extends ready generation over the full I/O space when = 1. (Default = 0) SPI Enables IILEGAL PIO detection for MIL-STD- 1750A spare I/O spaces. 1 = Spare I/O legal, 0 = Default = spare I/O illegal. CNF EDAC Function on MMU/COMBO; 1 = used, 0 = not used. EB1 Enable Block 1 of Unimplemented Memory, as Defined in the Unimplemented Memory Register. EB2 Enable Block 2 of Unimplemented Memory, as Defined in the Unimplemented Memory Register EIO Enable illegal PIO Detection, as defined in Last Implemented Input and Output Registers. LIO Enable Long I/O Ready Generation, 1ms to 15ms, I/O Addresses 0000-00FF, 8000- 80FF. LME Enable Long Memory Ready Generation, 1ms to 15ms, Addresses 0000-3FFF. STATUS REGISTER (Default = 0000) CPU CPU Passed PIC System Test. CMB COMBO Chip Passed PIC System Test. PIC PIC Chip Passed PIC System Test. STB Reserved. ADR Reserved. TWD Watch Dog reached terminal count. TBT Bus Time-out reached terminal count. IFL Interrupt Flag-Shows the last interrupt I/O command implemented in the software. MEMORY READY PROGRAM REGISTER (Default = FFFF) MEM Q1 Lower Block number of wait states. MEM Q2 Second Block number of wait states. MEM Q3 Third Block number of wait states. MEM Q4 Upper Block number of wait states. I/O READY PROGRAM REGISTER (Default = Undefined) IO Q1 Lower section number of wait states. IO Q2 Second section number of wait states. IO Q3 Third section number of wait states. IO Q4 Upper section number of wait states. PROGRAM REGISTER (Default = 0000) CFB 0:5, Clock Frequency Bits (MHz). EBT Enable Bus Time-out Function. SBT Select Bus Time-out Limit; 1 = 128 Cycles, 0 = 64 Cycles. EWD Enable Watch Dog Function. SWD Select Watch Dog Clock, 1 = 1KHz, 0 = 1MHz. WATCH DOG TIMER REGISTER (Default = 0000) BITS 0:15, Watch Dog set-up Count. UNIMPLEMENTED MEMORY REGISTER (Default = Undefined) BL1 LO Low boundary of unimplemented block 1 of memory. BL1 HI High boundary of unimplemented block 1 of memory. BL2 LO Low boundary of unimplemented block 2 of memory. BL2 HI High boundary of unimplemented block 2 of memory. FIRST UNIMPLEMENTED OUTPUT COMMAND REGISTER (Default = Undefined) BITS 0:5 Not used. BITS 6:15 First unused sequential PIO output command. FIRST UNIMPLEMENTED INPUT COMMAND REGISTER (Default = Undefined) BITS 0:5 Not used. BITS 6:15 First unused sequential PIO input command. FIRST FAILING REGISTER (Default = Undefined) BITS 0:15 16 LSB of the physical address of the first failure. |
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