PACE 1757 M/ME

Page 27 of 34

Document # MICRO-10 REV B

SIGNAL DESCRIPTIONS (Continued)

BUS STROBES AND QUALIFIERS

Mnemonic

Name

Description

STRBA (note 1)

Address Strobe

An active HIGH output that can be used to externally latch the contents

of IB(0:15) into the address latches of the PIC and MMU at the HIGH to

LOW transition of the strobe. The signal is tristate during bus cycles not

assigned to this CPU. It is issued by the CPU and input to the MMU and

PIC.

STRBD (note 2)

Data Strobe

An active LOW output used to read or write data from the PIC as well as

to strobe data in memory and XIO cycles. This signal is tri-state during

bus cycles not assigned to this CPU. It is interconnected in the same

manner as STRBA.

MEMW

Memory Write

An active LOW output produced in memory write cycles by the PIC.

Strobe

MEMR

Memory Read Strobe

An active LOW output produced by the P1754 in memory read cycles.

IOW

I/O Write Strobe

An active LOW output produced by the P1754 in output write cycles.

IOR

I/O Read Strobe

An active LOW output produced by the P1754 during input read cycles.

STRB EN

Strobe Enable

An active LOW input, enabling the active state of the address outputs of

the P1754 and the

MEMR, MEMW, IOR and IOW outputs. When a logic

"1" (if enabled by bits EST and EAD of the control register) it will

correspondingly tri-state the above signals.

INTA

Interrupt Acknowledge An active LOW output produced during any interrupt sequence

Strobe

corresponding to an output write to address 1000 (Hex).

DMA ACK

DMA Acknowledge

An active HIGH input from the DMA controller to the P1753 which

indicates a DMA cycle. Used to select the DMA table in the BPU memory

for protection. For example, this could allow the DMA channel to update

the program which could be write protected from the processor. In the

physical DMA mose, it will cause the Extended Address Liones (EXT

EX RDY

External Data Ready

An active HIGH output from the MMU that indicates no wait states are

requested. It becomes inactive for one clock (inserting one wait state)

whenever a memory page different than the current one is accessed (e.g.

a cache miss).

EX RDY1

External Data

An active LOW input to the PIC from the memory interface logic which at

Ready 1

a logical "1" overrides the internal RDYD generation and forces it to a

logical "0".

Note 1: One internal pulldown resistor is provided at the STRBA input. The nominal value is 40K Ohm and the maximum range is 20K Ohm to

80K Ohm. In designs with TTL devices loading STRBA, an additional external resistor may be required.

Note 2: One internal pullup is provided at the

STRBD input. The nominal value is 40K Ohms and the maximum range is 20K-80K Ohms.