PACE1757M datasheet(25/34 Pages) PYRAMID

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PACE 1757 M/ME

Page 25 of 34

Document # MICRO-10 REV B

SIGNAL DESCRIPTIONS (Continued)

FAULTS AND FLAGS

Mnemonic

Name

Description

MEM PRT ER

Memory Protect Error

An active-LOW input generated by the MMU or BPU, or both, during

attempted writes to protected memory. It is sampled by the

BUS BUSY

signal into the Fault Register (bit 0 CPU bus cycle, bit 1 if non-CPU bus

cycle). The error is generated in one of the following conditions: a

mismatch in the access keys in the MMU page, an access to an execution

protected page during instruction cycles, an access to a write protected

page during data cycles or an access to a page write protected by the

BPU.

MEM PAR ER

Memory Parity Error

An active LOW signal which is sampled by the

BUS BUSY signal into bit

2 of the CPU's Fault Register. It signals an error on the Data Bus during

a memory cycle. Two detection modes can be selected by programming

the control register of the MMU/COMBO: EDAC mode (6 Hamming code

parity bits) or single bit parity mode (even or odd parity). The signal is

inactive when none of the above modes are selected (default after reset).

EXT ADR ER IN

External Address

An active-LOW input sampled by the

BUS BUSY signal into the CPU

Error In

Fault Register (bit 5 or 8) depending on the cycle (memory or I/O).

EXT ADR ER OUT External Address

An active LOW output which signals to the CPU and memory interface

Error Out

logic that an unimplemented memory or illegal I/O access has taken

place.

SYSFLT0 -

System Fault 0,

Asynchronous, positive edge sensitive inputs that set bit 7 (SYSFLT0)

SYSFLT1

System Fault 1

or bits 13 and 15 (SYSFLT1) in the P1750A/AE Fault Register.

EX AD ER /

Illegal Address Error /

An active LOW output from the PIC indicating an illegal address error

SING ERR

Single Error

when referencing memory or I/O. It becomes an active HIGH input called

SINGLE ERROR for handshaking with the P1753 when the PIC is

programmed to support EDAC. Default state after reset is high impedance.

WR PROT /

Write Protected /

Either an active LOW output (

WR PROT, following STRBD timing)

PROT FLAG

Protection Flag

during legal memory write cycles when no protection occurs, or an active

high (PROT FLAG) signal indicating a protection error in a write cycle.

Either mode can be selected by programming the COMBO control

ME PA ER /

Memory Parity Error

An active LOW output indicating a Parity error when reading from

RAMDIS

memory. It becomes an active HIGH output called RAM DISABLE for

handshaking with the P1753 when the PIC is programmed to support

EDAC.

Terminal Count

An active HIGH output from the PIC indicating a bus time out or a

watchdog trigger.

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