PACE1757M datasheet(22/34 Pages) PYRAMID

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PACE 1757 M/ME

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Document # MICRO-10 REV B

SIGNAL DESCRIPTIONS

CLOCKS AND EXTERNAL REQUESTS

Mnemonic

Name

Description

CPU CLK

CPU clock

A single phase input clock signal (0-40 MHz, 40 percent to 60 percent duty

cycle. This is a common input to all 3 devices.

RESET

Reset

An active LOW input that initializes the device. Input to the P1750A/AE,

P1753 and P1754.

CON REQ

Console request

An active LOW input that initiates console operations after completion of

the current instruction. Input to the CPU.

INTERRUPT INPUTS

Mnemonic

Name

Description

PWRDN INT

Power down interrupt

An interrupt request input that cannot be masked or disabled. This signal

is active on the positive going edge or the high level, according to the

interrupt mode bit in the configuration register of the P1750A/AE.

USR0INT -

User interrupt

Interrupt request input signals that are active on the positive going edge

USR5INT

edge or the high level, according to the interrupt mode bit in the configuration

IOL1INT -

I/O Level Interrupts

Active HIGH interrupt requests that can be used to expand the number

IOL2INT

of user interrupts. Inputs to the P1750A/AE interrupt register.

ERROR CONTROL

Mnemonic

Name

Description

UNRCV ER

Unrecoverable error

An active HIGH output that indicates the occurrence of an error classified

as unrecoverable. A signal from the CPU.

MAJ ER

Major error

An active HIGH output that indicates the occurrence of an error classified

as major. A signal from the CPU.

DISCRETE CONTROL

Mnemonic

Name

Description

NML PWRUP

Normal power up

An active HIGH output that is set when the CPU has successfully

completed the built-in self test in the initialization sequence. It can be reset

by the I/O command RNS.

SNEW

Start new

An active HIGH output that indicates a new instruction is about to start

executing in the next cycle. This signal is issued by the CPU.

TRIGO RST

Trigger-go reset

An active LOW discrete output. This signal can be pulsed low under

program control I/O address 400B (Hex) and is automatically pulsed

during processor initialization.

STRT ROM

Start Up Rom

An output follow the execution of the ESUR and DSUR, I/O commands as

defined in MIL-STD-1750A. It will be at the logical level "1" after executing

ESUR and at the logical "0" level after executing DSUR. Initially, it defaults

to a "1" on the P1754.

DMA EN

Direct memory

An active HIGH output that indicates the DMA is enabled. It is

Access enable

disabled when the CPU is initialized (reset) and can be enabled or

disabled under program control (I/O commands DMAE, DMAD).

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