ST25R100 datasheet(84/86 Pages) STMICROELECTRONICS

84 / 86 page

Table 54.

Reserved ........................................................................ 52

Table 55.

Reserved ........................................................................ 52

Table 56.

Reserved ........................................................................ 52

Table 57.

Wake-up configuration register 1 ........................................................ 53

Table 58.

Typical wake-up period/time ........................................................... 53

Table 59.

Wake-up configuration register 2 ........................................................ 54

Table 60.

Measurement pulse length ............................................................ 54

Table 61.

I-Channel WU configuration register ...................................................... 54

Table 62.

I-Channel WU difference register ........................................................ 55

Table 63.

I-Channel WU display ADC register ...................................................... 55

Table 64.

I-Channel WU reference register ........................................................ 55

Table 65.

I-Channel WU display calibration register .................................................. 56

Table 66.

Q-Channel WU configuration register ..................................................... 56

Table 67.

Channel WU difference register ......................................................... 57

Table 68.

Q-Channel WU display ADC register ..................................................... 57

Table 69.

Q-Channel WU reference register ....................................................... 57

Table 70.

Q-Channel WU display calibration register ................................................. 58

Table 71.

TX frame register 1 ................................................................. 58

Table 72.

Tx frame register 2 .................................................................. 59

Table 73.

FIFO status register 1................................................................ 59

Table 74.

FIFO status register 2................................................................ 59

Table 75.

Collision display register .............................................................. 60

Table 76.

IRQ mask register 1 ................................................................. 60

Table 77.

IRQ mask register 2 ................................................................. 60

Table 78.

IRQ mask register 3 ................................................................. 61

Table 79.

IRQ status register 1 ................................................................ 61

Table 80.

IRQ status register 2 ................................................................ 62

Table 81.

IRQ status register 3 ................................................................ 62

Table 82.

IC identity register .................................................................. 62

Table 83.

Direct commands................................................................... 63

Table 84.

Observation access 1 ................................................................ 66

Table 85.

TAD1/TAD2 test mode ............................................................... 66

Table 86.

Observation register 2 ............................................................... 66

Table 87.

TAD1/TAD2 test signal (tm_rxwu_tad=3) ................................................... 67

Table 88.

TAD1/TAD2 test signal (tm_rxwu_tad=6) ................................................... 67

Table 89.

Absolute maximum ratings ............................................................ 68

Table 90.

Operating conditions ................................................................ 69

Table 91.

Characteristics of CMOS I/Os .......................................................... 70

Table 92.

Electrical characteristics (VDD = 2.7 V, VDD_IO = 2.7 V) ......................................... 71

Table 93.

Electrical characteristics (VDD = 3.3 V, VDD_IO = 3.3 V) ......................................... 72

Table 94.

Electrical characteristics (VDD = 5.5 V, VDD_IO = 5.5 V) ......................................... 73

Table 95.

SPI interface characteristics(up to 6 MHz) .................................................. 74

Table 96.

UFQFPN24 - Mechanical data .......................................................... 76

Table 97.

Ordering information scheme........................................................... 77

Table 98.

Document revision history ............................................................. 78

ST25R100

List of tables

DS14139 - Rev 5

page 84/86

ST25R100 датащи(PDF) 84 Page - STMicroelectronics

ST25R100 датащи(HTML) 84 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

датащи скачать

ссылки URL