ST25R100 datasheet(59/86 Pages) STMICROELECTRONICS

59 / 86 page

Table 72. Tx frame register 2

Bit Name Default

Function

Comment

ntx4

Number of full bytes to be transmitted (lsb)

ntx3

ntx2

ntx1

ntx0

nbtx2

Number of bits to transmit after the last full byte.

nbtx<2:0>=0 only full bytes to be transmitted.

Bit transmission starts from LSB. Applicable for

ISO14443A:

•

bit oriented anticollision frame in case the last

byte is a split byte

•

Tx is done without parity bit generation

nbtx1

nbtx0

5.13.55

FIFO status register 1

Address: 36h

Type: RO

Domain: RD

Table 73. FIFO status register 1

Bit

Name

Default

Function

Comment

fifo_b7

Number of bytes in the FIFO (LSB)

fifo_b<8:0> valid range is from 0 to 256

fifo_b6

fifo_b5

fifo_b4

fifo_b3

fifo_b2

fifo_b1

fifo_b0

5.13.56

FIFO status register 2

Address: 37h

Type: RO

Domain: RD

Table 74. FIFO status register 2

Bit Name Default

Function

Comment

RFU

fifo_b8

Number of bytes in the FIFO (msb)

fifo_unf

FIFO underflow

fifo_ovr

FIFO overflow

fifo_lb2

Number of bits in the last FIFO

byte if it was not complete

The received bits are stored in the LSB part of the last byte in the

FIFO.

In case of I_hfe, fifo_lb<2:0> shall be disregarded.

fifo_lb1

fifo_lb0

np_lb

Parity bit is missing in last byte

Set if the last byte was complete with 8 data bits and only the

parity bit is missing.

ST25R100

Application information

DS14139 - Rev 5

page 59/86

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