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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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C200 датащи(PDF) 4 Page - Intel Corporation |
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C200 датащи(HTML) 4 Page - Intel Corporation |
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4 / 82 page  Revision History 4 Specification Update Revision History Revision Description Date 001 • Initial Release January 2011 002 •Updated —Top Markings — PCH Device and Revision Identification •Added — Erratum 14: SATA Ports 2-5 Issue February 2011 003 •Updated —Top Markings — PCH Device and Revision Identification February 2011 004 •Added —Intel® Q65 Chipset to Top Markings and PCH Device and Revision Identification — Specification Change 1: Intel Q65 SKU Addition April 2011 005 •Removed — Specification Change 1 that went into Datasheet rev 003 •Added —Intel® C200 Series Chipsets to Top Markings, PCH Device and Revision Identification, and Errata April 2011 006 •Added —Intel® Z68 Chipset to Top Markings and PCH Device and Revision Identification May 2011 007 •Updated — Erratum 12: High-speed USB 2.0 Transmit Signal Amplitude •Added —Erratum 15: Intel® ME Clock Throttling Failure Causes Hang July 2011 008 •Updated — PCH Device and Revision Identification — Erratum 12 and USB terminology changed for consistency on various errata •Added — Errata 16: USB Full-/low-speed Port Reset or Clear TT Buffer Request and 17: Intel® 82579 Gigabit Ethernet Controller Transmission Issue — Specification Change 1: LED Locate Intel® Rapid Storage Technology Capability Removal — Specification Clarifications: 1: Device 31 Function 6 Disable Bit, 2: LAN Disable Reset, 3: SGPIO Signal Usage, 4: RTCRST# and SRTCRST# Clarification, 5: PPM of 25 MHz Option for CLKOUTFLEX2, 6: SATA Alternate ID Enable Definition Update, 7: SATA Hot Plug Operation, 8: GPIO13 Voltage Tolerance, and 9: EHCI Configuration Programming — Documentation Changes: 1: Addition of LPC Capability List Pointer Register, 2: Intel® Smart Response Technology Functional Description Updates, 3: Addition of Legacy ATA Backwards Compatibility Registers, 4: DMI L1 Exit Latency Documentation Change, 5: Device 30 Function 0 Naming Consistency Change, 6: Gigabit Ethernet Capabilities and Status Registers Additions, 7: Measured ICC Corrections, and 8: Miscellaneous Documentation Corrections August 2011 009 •Added — Specification Change: 2: Removal of S1 Support on Intel® C200 Series Chipset — Specification Clarifications: 10: PCH Thermal Sensor Temperature Range and 11: Secondary PCI Device Hiding Register Attribute Clarification — Documentation Changes: 9: 25 MHz Flex Clock AC Timings, 10: Fan Speed Control Signals Functional Description Introduction, 11: SMBus/SMLink Timing Naming Corrections, 12: PCI Express* Lane Reversal Bit Change, 13: Auxiliary Trip Point Lock Bit Correction, 14: Top Swap Updates, and 15: Miscellaneous Documentation Corrections II September 2011 010 •Updated — PCIe* PCH Device and Revision ID Table — Documentation Change: PCI Express* Lane Reversal Bit Change •Added — Specification Clarifications: 12: GPIO Lock Clarification and 13: GPIO13 Voltage Well — Documentation Change: 16: Ballout Documentation Changes October 2011 |
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