C200 datasheet(39/82 Pages) INTEL

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Specification Update

Specification Clarifications

e. Note 6 is added to the “Straight to S5 (Host Stays there) column in Table 5-38

Causes of Host and Global Resets:

6. Upon entry to S5, if Deep S4/S5 is enabled and conditions are met per section

5.13.7.6, the system will transition to Deep S4/S5.

f. Bits 11 and 8 of section 13.8.3.1 PM1_STS—Power Management 1 Status Register

are modified as shown.

18.

Power Management Clarifications

a. Clarify t200 timing by adding the following note to table 8-37:

Note: Measured from VccRTC-10% to RTCRST# reaching 55%*VccRTC. VccRTC is

defined as the final settling voltage that the rail ramps.

b. Delete t226 (in table 8-37, figure 8-1, and figure 8-2) as it is replaced by t200a.

c. t200a min timing is changed from 0 ms to 1 us.

Bit

Description

Power Button Override Status (PWRBTNOR_STS) — R/WC.

0 = Software clears this bit by writing a 1 to it.

1 = This bit is set any time a Power Button Override occurs (that is, the power button is

pressed for at least 4 consecutive seconds), due to the corresponding bit in the

SMBus slave message, Intel ME Initiated Power Button Override, Intel ME Initiated

Host Reset with Power down or due to an internal thermal sensor catastrophic

condition. The power button override causes an unconditional transition to the S5

state. The BIOS or SCI handler clears this bit by writing a 1 to it. This bit is not

affected by hard resets using CF9h writes, and is not reset by RSMRST#. Thus, this

bit is preserved through power failures. Note that if this bit is still asserted when

the global SCI_EN is set then an SCI will be generated.

NOTE: Upon entry to S5 due to an event described above, if Deep S4/S5 is enabled

and conditions are met per section 5.13.7.6, the system will transition to Deep

S4/S5.

Power Button Status (PWRBTN__STS) — R/WC. This bit is not affected by hard

resets caused by a CF9 write but is reset by DPWROK.

0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears

the PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to

the S5 state with only PWRBTN# enabled as a wake event.

This bit can be cleared by software by writing a one to the bit position.

1 = This bit is set by hardware when the PWRBTN# signal is asserted Low, independent

of any other enable bit.

In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or

SMI# if SCI_EN is not set) will be generated.

In any sleeping state S1–S5, while PWRBTN_EN (PMBASE + 02h, bit 8) and

PWRBTN_STS are both set, a wake event is generated.

NOTES:

If the PWRBTN_STS bit is cleared by software while the PWRBTN# signal is sell

asserted, this will not cause the PWRBN_STS bit to be set. The PWRBTN# signal

must go inactive and active again to set the PWRBTN_STS bit.

Upon entry to S5 due to a power button override, if Deep S4/S5 is enabled and

conditions are met per section 5.13.7.6, the system will transition to Deep

S4/S5.

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