C200 datasheet(76/82 Pages) INTEL

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Documentation Changes

Specification Update

33.

SPI Required Region Correction

The second paragraph of section 5.24.1.2.1 SPI Flash Regions is changed to the

following:

Only three masters can access the four regions: Host processor running BIOS code,

Integrated Gigabit Ethernet and Host processor running Gigabit Ethernet Software, and

Intel Management Engine. The Flash Descriptor and Intel ME region are the only

required regions. The Flash Descriptor has to be in Region 0 and Region 0 must be

located in the first sector of Device 0 (offset 10).

34.

High Precision Event Timers Functional Description

a. The following replaces section 5.17:

5.17 High Precision Event Timers (HPET)

This function provides a set of timers that can be used by the operating system. The

timers are defined such that the operating system may be able to assign specific timers

to be used directly by specific applications. Each timer can be configured to cause a

separate interrupt.

The PCH provides eight timers. The timers are implemented as a single counter, and

each timer has its own comparator and value register. The counter increases

monotonically. Each individual timer can generate an interrupt when the value in its

value register matches the value in the main counter.

The registers associated with these timers are mapped to a memory space (much like

the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS

reports to the operating system the location of the register space. The hardware can

support an assignable decode space; however, the BIOS sets this space prior to

handing it over to the operating system. It is not expected that the operating system

will move the location of these timers once it is set by the BIOS.

5.17.1 Timer Accuracy

1. The timers are accurate over any 1 ms period to within 0.05% of the time specified

in the timer resolution fields.

2. Within any 100 microsecond period, the timer reports a time that is up to two ticks

too early or too late. Each tick is less than or equal to 100 ns, so this represents an

error of less than 0.2%.

3. The timer is monotonic. It does not return the same value on two consecutive

reads (unless the counter has rolled over and reached the same value).

The main counter is clocked by the 14.31818 MHz clock. The accuracy of the main

counter is as accurate as the 14.31818 MHz clock.

5.17.2 Interrupt Mapping

The interrupts associated with the various timers have several interrupt mapping

options. When reprogramming the HPET interrupt routing scheme (LEG_RT_CNF bit in

the General Configuration Register), a spurious interrupt may occur. This is because the

other source of the interrupt (8254 timer) may be asserted. Software should mask

interrupts prior to clearing the LEG_RT_CNF bit.

Mapping Option #1 (Legacy Replacement Option)

In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is set. This forces the

mapping found in Table 5-41.

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