AX88796ALF datasheet(22/68 Pages) ASIX

22 / 68 page

AX88796ALF

3-in-1 Local Bus Fast Ethernet Controller

4.1.2 Multicast Address Match Filter

The Multicast Address Registers provide filtering of multicast addresses hashed by the CRC logic. All destination

addresses are fed through the 32 bits CRC generation logic and as the last bit of the destination address enters the CRC, the

6 most significant bits of the CRC generator are latched. These 6 bits are then decoded by a 1 of 64 decode to index a

unique filter bit (FB0-63) in the Multicast Address Registers. If the filter bit selected is set, the multicast packet is accepted.

The system designer would use a program to determine which filter bits to set in the multicast registers. All multicast filter

bits that correspond to Multicast Address Registers accepted by the node are then set to one. To accept all multicast packets

all of the registers are set to all ones.

MAR0

FB7

FB6

FB5

FB4

FB3

FB2

FB1

FB0

MAR1

FB15

FB14

FB13

FB12

FB11

FB10

FB9

FB8

MAR2

FB23

FB22

FB21

FB20

FB19

FB18

FB17

FB16

MAR3

FB31

FB30

FB29

FB28

FB27

FB26

FB25

FB24

MAR4

FB39

FB38

FB37

FB36

FB35

FB34

FB33

FB32

MAR5

FB47

FB46

FB45

FB44

FB43

FB42

FB41

FB40

MAR6

FB55

FB54

FB53

FB52

FB51

FB50

FB49

FB48

MAR7

FB63

FB62

FB61

FB60

FB59

FB58

FB57

FB56

If address Y is found to hash to the value 32 (20H), then FB32 in MAR2 should be initialized to ``1’’. This will cause the

AX88796A to accept any multicast packet with the address Y.

Although the hashing algorithm does not guarantee perfect filtering of multicast address, it will perfectly filter up to 64

logical address filters if these addresses are chosen to map into unique locations in the multicast filter.

Note: The first bit of received packet sequence is 1’s stands by Multicast Address.

32-bit CRC Generator

Latch

1 of 64 bit decoder

Filter bit array

X=31 to X=26

Clock

Selected bit

0 = reject, 1= accept

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