AX88796ALF datasheet(15/68 Pages) ASIX

15 / 68 page

AX88796ALF

3-in-1 Local Bus Fast Ethernet Controller

2.4 EEPROM Signals Group

SIGNAL

TYPE

PIN NO.

DESCRIPTION

EECS

EEPROM Chip Select: EEPROM chip select signal.

EECK

O/PD

EEPROM Clock: Signal connected to EEPROM clock pin.

EEDI

EEPROM Data In: Signal connected to EEPROM data input pin.

EEDO

I/PU

EEPROM Data Out: Signal connected to EEPROM data output pin.

TAB - 4 EEPROM bus interface signals group

2.5 MII Interface Signals Group (Optional)

SIGNAL

TYPE

PIN NO.

DESCRIPTION

RXD[3:0]

I/PU

98 – 95

Receive Data: RXD[3:0] is driven by the PHY synchronously with

respect to RX_CLK.

CRS

I/PD

100

Carrier Sense: Asynchronous signal CRS is asserted by the PHY when

either transmit or receive medium is non-idle.

RX_DV

I/PD

102

Receive Data Valid: RX_DV is driven by the PHY synchronously with

respect to RX_CLK. Asserted high when valid data is present on RXD

[3:0].

RX_CLK

I/PU

Receive Clock: RX_CLK is a continuous clock that provides the

timing reference for the transfer of the RX_DV, RXD[3:0] and RX_ER

signals from the PHY to the MII port of the repeater.

COL

I/PD

101

Collision: this signal is driven by PHY when collision is detected.

TX_EN

108

Transmit Enable: TX_EN is transition synchronously with respect to

the rising edge of TX_CLK. TX_EN indicates that the port is

presenting nibbles on TXD [3:0] for transmission.

TXD[3:0]

112 – 109

Transmit Data: TXD[3:0] is transition synchronously with respect to

the rising edge of TX_CLK. For each TX_CLK period in which

TX_EN is asserted, TXD[3:0] are accepted for transmission by the

PHY.

TX_CLK

I/PU

107

Transmit Clock: TX_CLK is a continuous clock from PHY. It provides

the timing reference for the transfer of the TX_EN and TXD[3:0]

signals from the MII port to the PHY.

MDC

O/PU

Station Management Data Clock: The timing reference for MDIO. All

data transfers on MDIO are synchronized to the rising edge of this

clock. The signal output reflects MDC register value. About MDC

MDC clock frequency is a 2.5MHz maximum accourding to IEEE

802.3u MII specification. Acturely, many PHYs are designed to accept

higher frequency than 2.5MHz.

MDIO

I/O/PU

Station Management Data Input/Output: Serial data input/output

transfers from/to the PHYs. The transfer protocol has to meet the IEEE

802.3u MII specification. For more information, please refer to section

6.5 CPU Access MII Station Management functions.

TAB - 5 MII interface signals group

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