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4571 датащи(PDF) 28 Page - Renesas Technology Corp |
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4571 датащи(HTML) 28 Page - Renesas Technology Corp |
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28 / 126 page ![]() Rev.1.02 May 25, 2007 Page 28 of 124 REJ03B0179-0102 4571 Group Fig 31. Timers structure (1) Data is set automatically from each reload register when timer underflows (auto-reload function). XIN ORCLK W50 0 1 D4/CNTR0 1/2 Port D4 output W52 0 1 W23 0 1 T1UDF T2UDF P20/INT0 I12 0 1 I11 0 1 One-sided edge detection circuit INTSNC I13 11 10 01 00 W21,W20 PWMOUT ORCLK T1UDF W22 Timer 2 (8) Reload register R2 (8) Register B (TAB2) (T2AB) Register A (T2AB) (T2AB) (TAB2) T2F Timer 2 interrupt T2UDF STCK 11 10 01 00 W11,W10 PWMOUT ORCLK CNTR0IN W12 W53 0 1 (Note 1) S R Q INT0SNC I10 W13 T1UDF Timer 1 (8) Reload register R1 (8) Register B (TAB1) (T1AB) Register A (T1AB) (T1AB) (TAB1) T1F Timer 1 interrupt T1UDF STCK PA1 1 0 00 01 10 11 MR3,MR2 Division circuit Divided by 8 Divided by 4 Divided by 2 Internal clock generating circuit (divided by 3) System clock (STCK) Instruction clock (INSTCK) Prescaler (8) PA0 Reload register RPS (8) Register B (TABPS) (TPSAB) Register A (TPSAB) (TPSAB) (TABPS) 1/4 PWMOUT: PWM signal (output from timer 3) CNTR0IN (TR1AB) Both edges detection circuit Note 1: Timer 1 count start synchronous circuit is synchronized with the valid edge of INT pin selected by bits 1 (I11) and 2 (I12) of register I1. |
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