4571 datasheet(63/126 Pages) RENESAS

63 / 126 page

Rev.1.02

May 25, 2007

Page 63 of 124

REJ03B0179-0102

4571 Group

CONTROL REGISTERS

Note 1.”R” represents read enabled, and “W” represents write enabled.

Note 2.When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.

Note 3.When the contents of I22 and I23 are changed, the external interrupt request flag EXF1 may be set.

Interrupt control register V1

at reset : 00002

at RAM back-up : 00002

R/W

TAV1/TV1A

V13

Timer 2 interrupt enable bit

Interrupt disabled (SNZT2 instruction is valid)

Interrupt enabled (SNZT2 instruction is invalid)

V12

Timer 1 interrupt enable bit

Interrupt disabled (SNZT1 instruction is valid)

Interrupt enabled (SNZT1 instruction is invalid)

V11

External 1 interrupt enable bit

Interrupt disabled (SNZ1 instruction is valid)

Interrupt enabled (SNZ1 instruction is invalid)

V10

External 0 interrupt enable bit

Interrupt disabled (SNZ0 instruction is valid)

Interrupt enabled (SNZ0 instruction is invalid)

Interrupt control register V2

at reset : 00002

at RAM back-up : 00002

R/W

TAV2/TV2A

V23

Voltage drop detector interrupt enable bit

Interrupt disabled (SNZVD instruction is valid)

Interrupt enabled (SNZVD instruction is invalid)

V22

Not used

This bit has no function, but read/write is enabled.

V21

Not used

This bit has no function, but read/write is enabled.

V20

Timer 3 interrupt enable bit

Interrupt disabled (SNZT3 instruction is valid)

Interrupt enabled (SNZT3 instruction is invalid)

Interrupt control register I1

at reset : 00002

at RAM back-up : state retained

R/W

TAI1/TI1A

I13

INT0 pin input control bit (Note 2)

INT0 pin input disabled

INT0 pin input enabled

I12

Interrupt valid waveform for INT0 pin/

return level selection bit (Note 2)

Falling waveform (“L” level of INT0 pin is recognized with the SNZI0

instruction)/“L” level

Rising waveform (“H” level of INT0 pin is recognized with the SNZI0

instruction)/“H” level

I11

INT0 pin edge detection circuit control bit

One-sided edge detected

Both edges detected

I10

INT0 pin

timer 1 control enable bit

Timer 1 disabled

Timer 1 enabled

Interrupt control register I2

at reset : 00002

at RAM back-up : state retained

R/W

TAI2/TI2A

I23

INT1 pin input control bit (Note 3)

INT0 pin input disabled

INT0 pin input enabled

I22

Interrupt valid waveform for INT1 pin/

return level selection bit (Note 3)

Falling waveform (“L” level of INT0 pin is recognized with the SNZI1

instruction)/“L” level

Rising waveform (“H” level of INT0 pin is recognized with the SNZI1

instruction)/“H” level

I21

INT1 pin edge detection circuit control bit

One-sided edge detected

Both edges detected

I20

Not used

This bit has no function, but read/write is enabled.

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