4571 datasheet(18/126 Pages) RENESAS

18 / 126 page

Rev.1.02

May 25, 2007

Page 18 of 124

REJ03B0179-0102

4571 Group

(4) Internal state during an interrupt

The internal state of the microcomputer during an interrupt is as

follows (Figure 20).

• Program counter (PC)

An interrupt address is set in program counter. The address to

b e ex ec u t e d wh e n re t u rn in g to the mai n rout ine is

automatically stored in the stack register (SK).

• Interrupt enable flag (INTE)

INTE flag is cleared to “0” so that interrupts are disabled.

• Interrupt request flag

Only the request flag for the current interrupt source is cleared

to “0” (the voltage drop detection circuit interrupt request flag

is excluded)

• Data pointer, carry flag, skip flag, registers A and B

The contents of these registers and flags are stored

automatically in the interrupt stack register (SDP).

(5) Interrupt processing

When an interrupt occurs, a program at an interrupt address is

executed after branching a data store sequence to stack register.

Write the branch instruction to an interrupt service routine at an

interrupt address. Use the RTI instruction to return from an

interrupt service routine.

Interrupt enabled by executing the EI instruction is performed

after executing 1 instruction (just after the next instruction is

executed). Accordingly, when the EI instruction is executed just

before the RTI instruction, interrupts are enabled after returning

the main routine. (Refer to Figure 19)

Fig 19. Program example of interrupt processing

Fig 20. Internal state when interrupt occurs

Fig 21. Interrupt system diagram

Main

routine

Interrupt

occurs

Interrupt is

enabled

Interrupt

service routine

RTI

: Interrupt enabled state

: Interrupt disabled state

Each interrupt address

• Program counter (PC)

The address of main routine to be

executed when returning

• Stack register (SK)

0 (Interrupt disabled)

• Interrupt enable flag (INTE)

0 (excluding voltage drop detection interrupt request flag)

• Interrupt request flag (only the flag for the current interrupt

source)

Stored in the interrupt stack register (SDP)

automatically

• Data pointer, carry flag, registers A and B, skip flag

EXF0

Request flag

(state retained)

V10

Enable bit

Enable flag

Address 0

in page 1

INT0 pin interrupt

waveform input

Timer 2

underflow

T1F

V12

Address 4

in page 1

Timer 1

underflow

T2F

V13

Address 6

in page 1

T3F

V20

Address 8

in page 1

Activated

condition

INTE

Timer 3

underflow

EXF1

V11

Address 2

in page 1

INT1 pin interrupt

waveform input

VDF

V23

Address E

in page 1

when supply voltage

goes lower than

specified value

4571 датащи(PDF) 18 Page - Renesas Technology Corp

4571 датащи(HTML) 18 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL