поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

ADAU1961WBCPZ-R7 датащи(PDF) 9 Page - Analog Devices

номер детали ADAU1961WBCPZ-R7
подробное описание детали  Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
PDF  73 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADAU1961WBCPZ-R7 датащи(HTML) 9 Page - Analog Devices

Back Button ADAU1961WBCPZ-R7 Datasheet HTML 5Page - Analog Devices ADAU1961WBCPZ-R7 Datasheet HTML 6Page - Analog Devices ADAU1961WBCPZ-R7 Datasheet HTML 7Page - Analog Devices ADAU1961WBCPZ-R7 Datasheet HTML 8Page - Analog Devices ADAU1961WBCPZ-R7 Datasheet HTML 9Page - Analog Devices ADAU1961WBCPZ-R7 Datasheet HTML 10Page - Analog Devices ADAU1961WBCPZ-R7 Datasheet HTML 11Page - Analog Devices ADAU1961WBCPZ-R7 Datasheet HTML 12Page - Analog Devices ADAU1961WBCPZ-R7 Datasheet HTML 13Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 73 page
background image
Data Sheet
ADAU1961
SPECIFICATIONS
analog.com
Rev. B | 9 of 73
Table 5. (Continued)
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
OUTPUT SPECIFICATIONS
Output Voltage High (VOH)
IOH = 2 mA @ 3.3 V
0.8 × IOVDD
V
Output Voltage Low (VOL)
IOL = 2 mA @ 3.3 V
0.1 × IOVDD
V
DIGITAL TIMING SPECIFICATIONS
−40°C < TA < +105°C, IOVDD = 3.3 V ± 10%.
Table 6. Digital Timing
Parameter
Limit
Unit
Description
tMIN
tMAX
MAIN CLOCK
tMP
74
488
ns
MCLK period, 256 × fS mode.
tMP
37
244
ns
MCLK period, 512 × fS mode.
tMP
24.7
162.7
ns
MCLK period, 768 × fS mode.
tMP
18.5
122
ns
MCLK period, 1024 × fS mode.
SERIAL PORT
tBIL
5
ns
BCLK pulse width low.
tBIH
5
ns
BCLK pulse width high.
tLIS
5
ns
LRCLK setup. Time to BCLK rising.
tLIH
5
ns
LRCLK hold. Time from BCLK rising.
tSIS
5
ns
DAC_SDATA setup. Time to BCLK rising.
tSIH
5
ns
DAC_SDATA hold. Time from BCLK rising.
tSODM
50
ns
ADC_SDATA delay. Time from BCLK falling in main mode.
SPI PORT
fCCLK
10
MHz
CCLK frequency.
tCCPL
10
ns
CCLK pulse width low.
tCCPH
10
ns
CCLK pulse width high.
tCLS
5
ns
CLATCH setup. Time to CCLK rising.
tCLH
10
ns
CLATCH hold. Time from CCLK rising.
tCLPH
10
ns
CLATCH pulse width high.
tCDS
5
ns
CDATA setup. Time to CCLK rising.
tCDH
5
ns
CDATA hold. Time from CCLK rising.
tCOD
50
ns
COUT three-stated. Time from CLATCH rising.
I2C PORT
fSCL
400
kHz
SCL frequency.
tSCLH
0.6
µs
SCL high.
tSCLL
1.3
µs
SCL low.
tSCS
0.6
µs
Setup time; relevant for repeated start condition.
tSCH
0.6
µs
Hold time. After this period, the first clock is generated.
tDS
100
ns
Data setup time.
tSCR
300
ns
SCL rise time.
tSCF
300
ns
SCL fall time.
tSDR
300
ns
SDA rise time.
tSDF
300
ns
SDA fall time.
tBFT
0.6
µs
Bus-free time. Time between stop and start.
DIGITAL MICROPHONE
RLOAD = 1 MΩ, CLOAD = 14 pF.
tDCF
10
ns
Digital microphone clock fall time.
tDCR
10
ns
Digital microphone clock rise time.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com