ADAU1961WBCPZ-R7 datasheet(25/73 Pages) AD

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Data Sheet

ADAU1961

CLOCKING AND SAMPLING RATES

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Rev. B | 25 of 73

PLL

The PLL uses the MCLK as a reference to generate the core clock.

PLL settings are set in Register R1 (PLL control register, Address

0x4002). Depending on the MCLK frequency, the PLL must be set

for either integer or fractional mode. The PLL can accept input

frequencies in the range of 8 MHz to 27 MHz.

All six bytes in the PLL control register must be written with a single

continuous write to the control port.

Figure 30. PLL Block Diagram

Integer Mode

Integer mode is used when the MCLK is an integer (R) multiple of

the PLL output (1024 × fS).

For example, if MCLK = 12.288 MHz and fS = 48 kHz, then

PLL required output = 1024 × 48 kHz = 49.152 MHz

R = 49.152 MHz/12.288 MHz = 4

In integer mode, the values set for N and M are ignored.

Fractional Mode

Fractional mode is used when the MCLK is a fractional (R + (N/M))

multiple of the PLL output.

For example, if MCLK = 12 MHz and fS = 48 kHz, then

PLL required output = 1024 × 48 kHz = 49.152 MHz

R + (N/M) = 49.152 MHz/12 MHz = 4 + (12/125)

Common fractional PLL parameter settings for 44.1 kHz and 48 kHz

sampling rates can be found in Table 15 and Table 16.

The PLL outputs a clock in the range of 41 MHz to 54 MHz, which

should be taken into account when calculating PLL values and

MCLK frequencies.

Table 14. PLL Control Register (Register R1, Address 0x4002)

Bits

Bit Name

Description

[47:32]

M[15:0]

Denominator of the fractional PLL: 16-bit binary number

0x00FD: M = 253 (default)

[31:16]

N[15:0]

Numerator of the fractional PLL: 16-bit binary number

0x000C: N = 12 (default)

[14:11]

R[3:0]

Integer part of PLL: four bits, only values 2 to 8 are valid

0010: R = 2 (default)

0011: R = 3

0100: R = 4

0101: R = 5

0110: R = 6

0111: R = 7

1000: R = 8

[10:9]

X[1:0]

PLL input clock divider

00: X = 1 (default)

01: X = 2

10: X = 3

11: X = 4

Type

PLL operation mode

0: Integer (default)

1: Fractional

Lock

PLL lock (read-only bit)

0: PLL unlocked (default)

1: PLL locked

PLLEN

PLL enable

0: PLL disabled (default)

1: PLL enabled

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