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ADAU1961WBCPZ-R7 датащи(PDF) 55 Page - Analog Devices

номер детали ADAU1961WBCPZ-R7
подробное описание детали  Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
PDF  73 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADAU1961WBCPZ-R7 датащи(HTML) 55 Page - Analog Devices

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Data Sheet
ADAU1961
CONTROL REGISTERS
analog.com
Rev. B | 55 of 73
Table 42. Converter Control 0 Register (Continued)
Bits
Bit Name
Description
4
DAOSR
DAC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
3
ADOSR
ADC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
[2:0]
CONVSR[2:0]
Converter sampling rate. The ADCs and DACs operate at the sampling rate set in this register. The converter rate selected is a ratio of
the base sampling rate, fS. The base sampling rate is determined by the operating frequency of the core clock. The serial port mirrors the
converter sampling rates set in this register.
Setting
Sampling Rate
Base Sampling Rate (fS = 48 kHz)
000
fS
48 kHz, base (default)
001
fS/6
8 kHz
010
fS/4
12 kHz
011
fS/3
16 kHz
100
fS/2
24 kHz
101
fS/1.5
32 kHz
110
fS/0.5
96 kHz
111
Reserved
R18: Converter Control 1, 16,408 (0x4018)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
ADPAIR[1:0]
Table 43. Converter Control 1 Register
Bits
Bit Name
Description
[1:0]
ADPAIR[1:0]
On-chip ADC serial data selection in TDM mode.
Setting
Pair
00
First pair (default)
01
Second pair
10
Third pair
11
Fourth pair
R19: ADC Control, 16,409 (0x4019)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
ADCPOL
HPF
DMPOL
DMSW
INSEL
ADCEN[1:0]
Table 44. ADC Control Register
Bits
Bit Name
Description
6
ADCPOL
Invert input polarity.
0 = normal (default).
1 = inverted.
5
HPF
ADC high-pass filter select. At 48 kHz, f3dB = 2 Hz.
0 = off (default).
1 = on.
4
DMPOL
Digital microphone data polarity swap.
0 = invert polarity.



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