ADAU1961WBCPZ-R7 datasheet(54/73 Pages) AD

номер детали	ADAU1961WBCPZ-R7

подробное описание детали	Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL

PDF	73 Pages

Scroll/Zoom	100%

производитель	AD [Analog Devices]

домашняя страница	http://www.analog.com

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54 / 73 page

Data Sheet

ADAU1961

CONTROL REGISTERS

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Rev. B | 54 of 73

Table 40. Serial Port Control 0 Register (Continued)

Bits

Bit Name

Description

1 = main mode.

R16: Serial Port Control 1, 16,406 (0x4016)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BPF[2:0]

ADTDM

DATDM

MSBP

LRDEL[1:0]

Table 41. Serial Port Control 1 Register

Bits

Bit Name

Description

[7:5]

BPF[2:0]

Number of bit clock cycles per LRCLK audio frame.

Setting

Bit Clock Cycles

000

64 (default)

001

010

011

128

100

256

101

Reserved

110

Reserved

111

Reserved

ADTDM

ADC serial audio data channel position in TDM mode.

0 = left first (default).

1 = right first.

DATDM

DAC serial audio data channel position in TDM mode.

0 = left first (default).

1 = right first.

MSBP

MSB position in the LRCLK frame.

0 = MSB first (default).

1 = LSB first.

[1:0]

LRDEL[1:0]

Data delay from LRCLK edge (in BCLK units).

Setting

Delay (Bit Clock Cycles)

1 (default)

R17: Converter Control 0, 16,407 (0x4017)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

DAPAIR[1:0]

DAOSR

ADOSR

CONVSR[2:0]

Table 42. Converter Control 0 Register

Bits

Bit Name

Description

[6:5]

DAPAIR[1:0]

On-chip DAC serial data selection in TDM mode.

Setting

Pair

First pair (default)

Second pair

Third pair

Fourth pair

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