PS200 datasheet(28/36 Pages) MICROCHIP

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PS200

DS21891B-page 26

TABLE 5-12:

A/D CONVERSION REQUIREMENTS

FIGURE 5-7:

A/D CONVERSION TIMING (SLEEP MODE)

Param

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

130*

TAD

A/D Clock Period

1.6

—

μsTOSC based, VREF ≥ 2.5V

3.0*

—

μsTOSC based, VREF full range

130*

TAD

A/D Internal RC

Oscillator Period

3.0*

6.0

9.0*

μs

ADCS<1:0> = 11 (RC mode)

At VDD = 2.5V

2.0*

4.0

6.0*

μsAt VDD = 5.0V

131*

TCNV

Conversion Time

(not including

acquisition time)(1)

—11 TAD

—TAD

Set GO bit to new data in

A/D Result register

132*

TACQ

Acquisition Time

—

11.5

—

μs

μs The minimum time is the amplifier

settling time. This may be used if

the “new” input voltage has not

changed by more than 1 LSb (i.e.,

1 mV @ 4.096V) from the last

sampled voltage (as stated on

CHOLD).

134*

TGO

Q4 to A/D Clock

Start

—TOSC/2

—

If the A/D clock source is selected

as RC, a time of TCY is added

before the A/D clock starts. This

allows the SLEEP instruction to be

executed.

These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25

°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1:

ADRES register may be read on the following TCY cycle.

131

130

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

Note 1:

If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP

instruction to be executed.

134

132

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