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PS200 датащи(PDF) 27 Page - Microchip Technology |
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PS200 датащи(HTML) 27 Page - Microchip Technology |
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27 / 36 page ![]() © 2005 Microchip Technology Inc. DS21891B-page 25 PS200 TABLE 5-11: A/D CONVERTER CHARACTERISTICS FIGURE 5-6: A/D CONVERSION TIMING (NORMAL MODE) Param No. Sym Characteristic Min Typ† Max Units Conditions A01 NR Resolution — — 10 bits bit A02 EABS Total Absolute Error*(1) —— ±1LSb VREF = 5.0V A03 EIL Integral Error — — ±1LSb VREF = 5.0V A04 EDL Differential Error — — ±1 LSb No missing codes to 10 bits, VREF = 5.0V A05 EFS Full-Scale Range 2.2* — 5.5* V A06 EOFF Offset Error — — ±1LSb VREF = 5.0V A07 EGN Gain Error — — ±1LSb VREF = 5.0V A10 — Monotonicity — guaranteed(2) —— VSS ≤ VAIN ≤ VREF A20 A20A VREF Reference Voltage 2.2(4) 2.5 —— VDD + 0.3 V Absolute minimum to ensure 10-bit accuracy A25 VAIN Analog Input Voltage VSS —VREF(5) V A30 ZAIN Recommended Impedance of Analog Voltage Source —— 10 k Ω A50 IREF VREF Input Current*(3) 10 — — — 1000 10 μA μA During VAIN acquisition. Based on differential of VHOLD to VAIN. During A/D conversion cycle. * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25 °C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes Integral, Differential, Offset and Gain Errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: VREF current is from external VREF or VDD pin, whichever is selected as reference input. 4: Only limited when VDD is at or below 2.5V. If VDD is above 2.5V, VREF is allowed to go as low as 1.0V. 5: Analog input voltages are allowed up to VDD, however, the conversion accuracy is limited to VSS to VREF. 131 130 132 Q4 A/D CLK A/D DATA ADRES ADIF GO SAMPLE OLD_DATA SAMPLING STOPPED DONE NEW_DATA 98 7 3 2 1 0 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 1/2 TCY 6 134 |
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