ST25R200 datasheet(19/88 Pages) STMICROELECTRONICS

19 / 88 page

Direct commands with immediate execution can be followed by another SPI mode (read, write, or FIFO) without

deactivating the BSS signal in between.

Figure 14. SPI communication: direct command chaining

BSS

DIRECT COMMAND

READ, WRITE or FIFO MODE

FIFO mode

Reading received data from the FIFO is similar to reading data from the addressable registers. Read and write

operations are performed by accessing the address 0x5F, resulting in 0x5F for a write operation and 0xDF for a

read operation.

Figure 15. SPI communication: writing bytes into FIFO

BSS

SCLK

MOSI

1 to 256

bytes

‘0’ Write

Start of

payload Data

0x5F FIFO

Figure 16. SPI communication: reading bytes from FIFO

BSS

SCLK

MOSI

1 to 256

bytes

tristate

MISO

SCLK rising edge

Data is moved

from FIFO

SCLK falling edge Data

is transfered to µC

‘1’ Read

0x5F FIFO

5.8.3

FIFO block

The ST25R200 features a 256 bytes FIFO. The control logic shifts the data during transmission, which was

previously loaded by the external host to the framing block and further to the transmitter. During reception, the

demodulated data is stored in the FIFO and the host can receive data at a later moment.

The FIFO status register 2 also contains two bits that indicate that the FIFO was not correctly served during the

transmission or reception process (FIFO overflow and FIFO underflow).

A FIFO overflow is set when too much data is written into the FIFO.

When this bit is set during Rx, the external controller did not react on time on the water level IRQ and more than

256 bytes were written into the FIFO. Consequently, the received data is corrupted.

When an overflow happens during transmission, it means that the controller has written more data than the FIFO

size. The data to be transmitted is corrupted.

ST25R200

Application information

DS13658 - Rev 2

page 19/88

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