ST25R200 datasheet(15/88 Pages) STMICROELECTRONICS

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5.6

Crystal oscillator

The crystal oscillator operates with 27.12 MHz crystals. The operation of the quartz crystal oscillator is enabled

when the option bit en is set to one.

The oscillator is based on an inverter stage supplied by the controlled current source. A feedback loop is

controlling the bias current to regulate the amplitude on XTI/XTO pins to approximately 1 Vpp.

Division by two assures that the 13.56 MHz signal has a duty cycle of 50%, which is better for the transmitter

performance (no PW distortion).

The ADC and preprocessing block are clocked directly with 27.12 MHz. All other blocks operate at 13.56 MHz or

lower, generated in the main logic. An interrupt (I_osc) is sent to inform the host that stable oscillator operation is

reached.

The status of the oscillator can be observed by checking the osc_ok display bit. This bit is set to one when the

oscillator frequency is stable.

5.7

RC oscillator

RC oscillator is used to support the low power WU mode, and it runs at the frequency of 26.48 kHz nominal. It is

enabled when the device enters the WU mode, and is disabled when the device goes to PD or RD mode.

Additionally, it may be enabled by execution of the direct command start wake-up timer.

5.8

Communication with an external host

The ST25R200 communicates with a host via an SPI interface where it acts as a peripheral device, relying on the

host to initiate all communication.

To notify the host of completed commands or external events that the ST25R200 signals an interrupt on the IRQ

pin.

A RESET pin is also available to reset the device logic.

5.8.1

Interrupt interface

There are three interrupt registers implemented in the ST25R200.

When an interrupt condition is met, the source of the interrupt bit is set and the IRQ pin transitions to high.

In order to distinguish between different interrupt sources the host reads the interrupt registers. After a particular

interrupt register is read, its content is reset to 0.

The IRQ pin transitions to low after the interrupt bit(s) that caused its transition to high has(have) been read.

Note:

There may be more than one interrupt bit set if the host does not immediately read the interrupt registers after

the IRQ signal is set and another event causing an interrupt occurs. In this case, the IRQ pin transitions to low

after the last bit causing the interrupt is read.

If an interrupt from a certain source is not required, it can be disabled by setting the corresponding bit in the mask

interrupt registers. In the case of masking a certain interrupt source the IRQ line is not set high, but the interrupt

status bit is still set in the IRQ status registers.

By reading the IRQ status registers, the masked interrupt bits are also retrieved and cleared.

In case an interrupt is masked and its bit set to high due to a previous IRQ event, and then the host unmasked

this particular IRQ source, the IRQ line is immediately set to high. This notifies the host system that there are

some interrupt events not yet read out.

5.8.2

Serial peripheral interface (SPI)

The ST25R200 has a standard serial peripheral interface with clock polarity of 0, a clock phase of 1, and an active

low slave select signal. The communication starts with the master pulling BSS low. The MOSI pin is sampled on

the falling edge of SCLK, and the state of the MISO pin is updated on the rising edge of the SCLK signal. The

data is transferred byte-wise, the most significant bit first. The read and write commands support an address auto

increment to reduce communication time.

ST25R200

Application information

DS13658 - Rev 2

page 15/88

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