ST25R200 datasheet(14/88 Pages) STMICROELECTRONICS

14 / 88 page

Figure 7 details the building blocks of the ST25R200 power supply system. It contains three regulators, a

power

‑down support block, a block generating analog reference voltage (AGDC), and a block performing the

automatic power supply adjustment procedure. The three regulators are providing supply to analog blocks

(VDD_A), logic (VDD_D), and transmitter (VDD_DR).

VDD_A and VDD_D regulators

VDD_A and VDD_D regulators are used to supply the ST25R200 analog and digital blocks respectively.

In power

‑down and wake‑up modes, the VDD_D is in low power and is maintained by the power‑down support

block. In ready mode, the VDD_D is in normal mode and is supplied by the VDD_D regulator.

VDD_A is available in RD mode through the VDD_A regulator.

VDD_DR regulator

The purpose of this regulator is to improve the PSRR (power supply rejection ratio) of the transmitter (the noise of

the transmitter power supply is emitted and fed back to the receiver).

The VDD_DR regulator operation is controlled and observed by accessing three regulator registers: general

configuration, regulator configuration, and display register1.

Bit reg_s controls the regulator mode.

When the bit reg_s is asserted to 1, the regulated voltage is defined by the bits rege<4:0>.

If it is set to 0 (default state), the regulated voltage is expressed by a target drop from VDD defined in bits

regd<2:0> and by using direct command adjust regulators.

The regulated voltage adjustment range depends on the power supply.

The actual-regulated settings can be observed in bits regc<4:0>.

The VDD_DR regulator includes a current limiter that limits the regulator current to 250 mA in normal operation.

The bit i_lim is set when the VDD_DR regulator is in current limiting mode.

In power

‑down mode, the VDD_DR regulator is not operating. Output is connected to VDD through the 1 kΩ

resistor.

VDD_AM regulator

This regulator is used to support the transmitter AM modulation. Its output voltage is used as a transmitter supply

during the modulation phase. The output is internally connected to the transmitter. It requires decoupling

capacitors at the VDD_AM pin.

VDD_DR is used as a reference voltage, resulting in the correct VDD_AM voltage and modulation index across

the supply voltage range.

The output voltage and therefore the modulation setting is controlled by the am_mod<3:0> option bits from 8 to

55% in 16 steps.

In PD mode, the VDD_AM regulator is not operating. The VDD_AM pin is connected to the VDD through a 1 kΩ

resistor.

Note:

The actual modulation index may deviate from the target set by am_mod<3:0> when considerable RFO driver

resistance is added via d_res<3:0>.

5.4

Power-down support block

In PD mode the regulators are disabled to save current. In this mode, a low-power power

‑down support block

maintains the VDD_D.

5.5

Automatic adjust regulator circuit

The device has the capability to adjust the VDD_DR (and VDD_A) regulator voltage drop to a defined target drop.

Using this method, the PSRR is optimized and the maximum available driver supply is used. The adjustment

procedure is detailed in Section 5.15.5: Adjust regulators.

ST25R200

Application information

DS13658 - Rev 2

page 14/88

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