AM79C940 datasheet(55/144 Pages) AMD

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Am79C940

subsequent packets that would have normally been

passed to the host, and are now ignored due to the

disabled state of the receiver.

Note that clearing the ENRCV bit disables the asser-

tion of RDTREQ. If ENRCV is cleared during receive

activity and remains cleared for a long time and if the

tail end of the receive frame currently in progress is

longer than the amount of space available in the

Receive FIFO, Receive FIFO overflow will occur. How-

ever, even with RDTREQ deasserted, if there is valid

data in the Receive FIFO to be read, successful slave

reads to the Receive FIFO can be executed (indicated

by valid DTV). It is the host’s responsibility to avoid the

overflow situation.

Automatic Pad Stripping

During reception of a frame, the pad field can be

stripped automatically. ASTRP RCV = 1 enables the

automatic pad stripping feature. The pad field will be

stripped before the frame is passed to the FIFO, thus

preserving FIFO space for additional frames. The FCS

field will also be stripped, since it is computed at the

transmitting station based on the data and pad field

characters, and will be invalid for a receive frame that

has the pad characters stripped.

The number of bytes to be stripped is calculated from

the embedded length field (as defined in the IEEE

802.3 definition) contained in the packet. The length

indicates the actual number of LLC data bytes con-

tained in the message. Any received frame which con-

tains a length field less than 46 bytes will have the pad

field stripped. Receive frames which have a length field

of 46 bytes or greater will be passed to the host

unmodified.

Since any valid Ethernet Type field value will always be

greater than a normal 802.3 Length field, the MACE

device will not attempt to strip valid Ethernet frames.

Note that for some network protocols, the value passed

in the Ethernet Type and/or 802.3 Length field is not

compliant with either standard and may cause

problems.

The diagram below shows the byte/bit ordering of the

received length field for an 802.3 compatible frame

format.

Receive FCS Checking

Reception and checking of the received FCS is per-

formed automatically by the MACE device. Note that if

the Automatic Pad Stripping feature is enabled,

the received FCS will be verified against the value

computed for the incoming bit stream including pad

characters, but it will not be passed through the Re-

ceive FIFO to the host. If an FCS error is detected, this

will be reported by the FCS bit (bit 4) in the Receive

Frame Status.

Receive Status Information

The EOF indication signals that the last byte/word of

data has been passed from the FIFO for the specific

frame. This will be accompanied by a RCVINT indica-

tion in the the Interrupt Register signaling that the

Receive Frame Status has been updated, and must be

Preamble

1010....1010

SYNCH

10101011

Dest.

ADDR.

SRCE.

ADDR.

Length

LLC

DATA

Pad

FCS

Bits

Bytes

46–1500

Bytes

Most

Significant

Byte

Least

Significant

Byte

Bit

Start of Packet

at Time= 0

Increasing Time

Bit

45–0

Bytes

1–1500

Bytes

16235D-9

802.3 Packet and Length Field Transmission Order

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