AM79C940 datasheet(33/144 Pages) AMD

33 / 144 page

Am79C940

TDTREQ would remain de-asserted. Hence for byte

wide data transfers, the XMTFW should be pro-

grammed to the 8 or 16 write cycle limit, or the host

should ensure that sufficient data will be written to the

XMTFIFO after TDTREQ has been de-asserted (which

is permitted), to guarantee that the transmission will

commence. A third alternative is to program the Trans-

mit Start Point (XMTSP) in the BIU Configuration Con-

trol register to below the 64-byte default; thereby

imposing a lower latency to the host system requiring

additional data to ensure the XMTFIFO does not

underflow during the transmit process, versus using

the default XMTSP value. Note that if 64 single byte

writes are executed on the XMTFIFO, and the XMTSP

is set to 64-bytes, the transmission will commence, and

all 64-bytes of information will be accepted by

the XMTFIFO.

The number of write cycles that the host uses to write

the packet into the Transmit FIFO will also directly in-

fluence the amount of space utilized by the transmit

message. If the number of write cycles (n) required to

transfer a packet to the Transmit FIFO is even, the

number of bytes used in the Transmit FIFO will be 2*n.

If the number of write cycles required to transfer a

packet to the Transmit FIFO is odd, the number of

bytes used in the Transmit FIFO will be 2*n + 2 be-

cause the End Of Frame indication in the XMTFIFO is

always placed at the end of a 4-byte boundary. For ex-

ample, a 32-byte message written as bytes (n = 32 cy-

cles) will use 64-bytes of space in the Transmit FIFO

(2*n = 64), whereas a 65-byte message written as 32

words and 1 byte (n = 33 cycles) would use 68-bytes

(2*n + 2 = 68) .

The Transmit FIFO has been sized appropriately to

minimize the system interface overhead. However,

consideration must be given to overall system design if

byte writes are supported. In order to guarantee that

sufficient space is present in the XMTFIFO to accept

the number of write cycles programmed by the XMTFW

(including an End Of Frame delimiter), TDTREQ may

go inactive before the XMTSP threshold is reached

when using the non burst mode (XMTBRST = 0). For

instance, assume that the XMTFW is programmed to

allow 32 write cycles (default), and XMTSP is pro-

grammed to require 64 bytes (default) before starting

transmission. Assuming that the host bursts the trans-

mit data in a 32 cycle block, writing a single byte any-

where within this block will mean that XMTSP will not

have been reached. This would be a typical scenario if

the transmit data buffer was not aligned to a word

boundary. The MACE device will continue to assert

TDTREQ since an additional 36 write cycles can still be

executed. If the host starts a second burst, the XMTSP

will be reached, and TDTREQ will deassert when less

that 32 write cycle can be performed although the data

written by the host will continue to be accepted.

The host must be aware that additional space exists in

the XMTFIFO although TDTREQ becomes inactive,

and must continue to write data to ensure the XMTSP

threshold is achieved. No transmit activity will com-

mence until the XMTSP threshold is reache d.

Once 36 write cycles have been executed.

Note that write cycles can be performed to the XMT-

FIFO even if the TDTREQ is inactive. When TDTREQ

is asserted, it guarantees that a minimum amount of

space exists, when TDTREQ is deasserted, it does not

necessarily indicate that there is no space in the XMT-

FIFO. The DTV pin will indicate the successful accep-

tance of data by the Transmit FIFO.

As another example, assume again that the XMTFW is

programmed for 32 write cycles. If the host writes word

wide data continuously to the XMTFIFO, the TDTREQ

will deassert when 36 writes have executed on the

XMTFIFO, at which point 72-bytes will have been writ-

ten to the XMTFIFO, the 64-byte XMTSP will have

been exceeded and the transmission of preamble will

have commenced. TDTREQ will not re-assert until the

transmission of the packet data has commenced and

the possibility of losing data due to a collision within the

slot time is removed (512 bits have been transmitted

without a collision indication). Assuming that the host

actually stopped writing data after the initial 72-bytes,

there will be only 16-bytes of data remaining in the

XMTFIFO (8-bytes of preamble/SFD plus 56-bytes of

data have been transmitted), corresponding to 12.8

µs

of latency before an XMTFIFO underrun occurs. This

latency is considerably less than the maximum possi-

ble 57.6

µs the system may have assumed. If the host

had continued with the block transfer until 64 write

cycles had been performed, 128-bytes would have

been written to the XMTFIFO, and 72-bytes of latency

would remain (57.6

µs) when TDTREQ was re-as-

serted.

Transmit FIFO—Burst Operation

The XMTFIFO burst mode, programmed by the XMT-

BRST bit in the FIFO Configuration Control register,

modifies TDTREQ behavior. The assertion of TDTREQ

is controlled by the programming of the XMTFW bits,

such that when the specified number of write cycles

can be guaranteed (8, 16 or 32), TDTREQ will be as-

serted. TDTREQ will be de-asserted when the

XMT FIFO can only accept a single write cycle (one

word write including an End Of Frame delimiter) allow-

ing the external device to burst data into the XMTFIFO

when TDTREQ is asserted, and stop when TDTREQ

is deasserted.

Receive FIFO—General Operation

The Receive FIFO contains additional logic to ensure

that sufficient data is present in the RCVFIFO to allow

the specified number of bytes to be read, regardless of

the ordering of byte/word read accesses. This has an

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