AM79C940 datasheet(35/144 Pages) AMD

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Am79C940

prior to the termination of reception must be read from

the RCVFIFO before the RCVFS bytes are available.

Media Access Control (MAC)

The Media Access Control engine is the heart of the

MACE device, incorporating the essential protocol

requirements for operation of a compliant Ethernet/

802.3 node, and providing the interface between the

FIFO sub-system and the Manchester Encoder/

Decoder (MENDEC).

The MAC engine is fully compliant to Section 4 of ISO/

IEC 8802-3 (ANSI/IEEE Standard 1990 Second edi-

tion) and ANSI/IEEE 802.3 (1985).

The MAC engine provides enhanced features, pro-

grammed through the Transmit Frame Control and

Receive Frame Control registers, designed to minimize

host supervision and pre or post message processing.

These features include the ability to disable retries after

a collisio n, dyna mic FC S gen erati on on a

packet-by-packet basis, and automatic pad field

insertion and deletion to enforce minimum frame

size attributes.

The two primary attributes of the MAC engine are:

s Transmit and receive message data encapsulation

— Framing (frame boundary delimitation, frame

synchronization)

— Addressing (source and destination address

handling)

— Error detection (physical medium transmission

errors)

s Media access management

— Medium allocation (collision avoidance)

— Contention resolution (collision handling)

Transmit and Receive Message Data

Encapsulation

Data passed to the MACE device Transmit FIFO will be

assumed to be correctly formatted for transmission

over the network as a valid packet. The user is required

to pass the data stream for transmission to the MACE

chip in the correct order, according to the byte ordering

convention programmed for the BIU.

The MACE device provides minimum frame size

enforcement for transmit and receive packets. When

APAD XMT = 1 (default), transmit messages will be

padded with sufficient bytes (containing 00h) to ensure

that the receiving station will observe an information

field (destination address, source address, length/type,

data and FCS) of 64-bytes. When ASTRP RCV = 1

(default), the receiver will automatically strip pad and

FCS bytes from the received message if the value in

the length field is below the minimum data size

(46-bytes). Both features can be independently

over-ridden to allow illegally short (less than 64-bytes

of pa ck et data ) m e ss age s to b e tr a n sm itte d

and/or received.

Framing (Frame Boundary Delimitation,

Frame Synchronization)

The MACE device will autonomously handle the con-

struction of the transmit frame. When the Transmit

FIFO has been filled to the predetermined threshold

(set by XMTSP), and providing access to the channel

is currently permitted, the MACE device will commence

the 7 byte preamble sequence (10101010b, where first

bit transmitted is a 1). The MACE device will subse-

quently append the Start Frame Delimiter (SFD) byte

(10101011) followed by the serialized data from the

Transmit FIFO. Once the data has been completed, the

MACE device will append the FCS (most significant bit

first) computed on the entire data portion of the

message.

Note that the user is responsible for the correct order-

ing and content in each of the fields in the frame,

including the destination address, source address,

length/type and packet data.

The receive section of the MACE device will detect an

incoming preamble sequence and lock to the encoded

clock. The internal MENDEC will decode the serial bit

stream and present this to the MAC engine. The MAC

will discard the first 8-bits of information before search-

ing for the SFD sequence. Once the SFD is detected,

all subsequent bits are treated as part of the frame. The

MACE device will inspect the length field to ensure

minimum frame size, strip unnecessary pad characters

(if enabled), and pass the remaining bytes through the

Receive FIFO to the host. If pad stripping is performed,

the MACE device will also strip the received FCS

bytes, although the normal FCS computation and

checking will occur. Note that apart from pad stripping,

the frame will be passed unmodified to the host. If the

length field has a value of 46 or greater, the MACE de-

vice will not attempt to validate the length against the

number of bytes contained in the message.

If the frame terminates or suffers a collision before

64-bytes of information (after SFD) have been

received, the MACE device will automatically delete

the frame from the Receive FIFO, without host inter-

vention. Note however, that if the Low Latency Receive

option has been enabled (LLRCV = 1 in the Receive

Frame Control register), the MACE device will not

delete receive frames which experience a collision

once the 12-byte low watermark has been reached

(see the FIFO Sub-System section for additional

details).

Addressing (Source and Destination

Address Handling)

The first 6-bytes of information after SFD will be inter-

preted as the destination address field. The MACE

device provides facilities for physical, logical and

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