AM79C940 datasheet(52/144 Pages) AMD

52 / 144 page

Am79C940

mit FIFO will not be overwritten until at least 64 bytes

(512 bits) of data have been successfully transmitted

onto the network. This criteria will be met, regardless of

whether the transmit frame was the first (or only) frame

in the Transmit FIFO, or if the transmit frame was

queued pending completion of the preceding frame.

(b) If 16 total attempts (initial attempt plus 15 retries)

have been made to transmit the frame, the MACE

device will abandon the transmit process for the partic-

ular frame, de-assert the TDTREQ pin, report a Retry

Error (RTRY) in the Transmit Frame Status, and set the

XMTINT bit in the Interrupt Register, causing activation

of the external INTR pin providing the interrupt is

unmasked.

Once the XMTINT condition has been externally recog-

nized, the Transmit Frame Counter (XMTFC) can be

read to determine whether the tail end of the frame that

suffers the RTRY error is still in the host memory (i.e.,

when XMTFC = 0). This XMTFC read should be

requested before the Transmit Frame Status read

since reading the XMTFS would cause the XMTFC to

decrement. If the tail end of the frame is indeed still in

the host memory, the host is responsible for ensuring

that the tail end of the frame does not get written into

the FIFO and does not get transmitted as a whole

frame. It is recommended that the host clear the tail

end of the frame from the host memory before request-

ing the XMTFS read so that after the XMTFS read,

when MACE device re-asserts TDTREQ, the tail end of

the frame does not get written into the FIFO. The

Transmit Frame Status read will indicate that the RTRY

error occurred. The read operation on the Transmit

Frame Status will update the FIFO read and write

pointers. If no End-of-Frame write (EOF pin assertion)

had occurred during the FIFO write sequence, the en-

tire transmit path will be reset (which will update the

Transmit FIFO watermark with the current XMTFW

value in the FIFO Configuration Control register). If a

whole frame does reside in the FIFO, the read pointer

will be moved to the start of the next frame or free loca-

tion in the FIFO, and the write pointer will be unaf-

fected. TDTREQ will not be re-asserted until the

Transmit Frame Status has been read.

After a RTRY error, all further packet transmission will

be suspended until the Transmit Frame Status is read,

regardless of whether additional packet data exists in

the FIFO to be transmitted. Receive FIFO read opera-

tions are not impaired.

Packets experiencing 16 unsuccessful attempt to

transmit will not be re-tried. Recovery from this condi-

tion must be performed by upper layer software.

Abnormal network conditions include:

(a)

Loss of carrier.

(b)

Late collision.

(c)

SQE Test Error.

These should not occur on a correctly configured 802.3

network, but will be reported if the network has been

incorrectly configured or a fault condition exists.

(a) A loss of carrier condition will be reported if the

MACE device cannot observe receive activity while it is

transmitting. After the MACE device initiates a trans-

mission it will expect to see data looped-back on the

receive input path. This will internally generate a carrier

sense, indicating that the integrity of the data path to

and from the external MAU is intact, and that the MAU

is operating correctly.

When the AUI port is selected, if carrier sense does not

become active in response to the data transmission, or

becomes inactive before the end of transmission, the

loss of carrier (LCAR) error bit will be set in the Trans-

mit Frame Status (bit 7) after the packet has been

transmitted. The packet will not be re-tried on the basis

of an LCAR error.

When the 10BASE–T port is selected, LCAR will be

reported for every packet transmitted during the Link

fail condition.

When the GPSI port is selected, LCAR will be reported

if the RXCRS input pin fails to become active during a

transmission, or once active, goes inactive before the

end of transmission.

When the DAI port is selected, LCAR errors will not

occur, since the MACE device will internally loop back

the transmit data path to the receiver. The loop back

feature must not be performed by the external trans-

ceiver when the DAI port is used.

During internal loopback, LCAR will not be set, since

the MACE device has direct control of the transmit and

receive path integrity. When in external loopback,

LCAR will operate normally according to the specific

port which has been selected.

(b) A late collision will be reported if a collision condition

exists or commences 64 byte times (512 bit times) after

the transmit process was initiated (first bit of preamble

commenced). The MACE device will abandon the

transmit process for the particular frame, complete

transmission of the jam sequence (32-bit all zeroes

pattern), de-assert the TDTREQ pin, report the Late

Collision (LCOL) and Transmit Status Valid (XMTSV) in

the Transmit Frame Status, and set the XMTINT bit in

the Interrupt Register, causing activation of the external

INTR pin providing the interrupt is unmasked.

Once the XMTINT condition has been externally recog-

nized, the Transmit Frame Counter (XMTFC) can be

read to determine whether the tail end of the frame that

suffers the LCOL error is still in the host memory (i.e.,

when XMTFC = 0). This XMTFC read should be

requested before the Transmit Frame Status read

since reading the XMTFS would cause the XMTFC to

decrement. If the tail end of the frame is indeed still in

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