1999 June 10

11

Philips Semiconductors

Preliminary specification

5 V spindle & VCM driver combo

TDA5345HT

Table 2

Serial Interface REGISTERS floorplan

Note:

1. [1] (or [0]) means that the bit is set to 1 (or 0) when PorN is low => default value at power up.

2. Use register 7 (Dac12a) for low VCM loop gain and register 8 (Dac12b) for high gain.

Control bits:

Bits [11, 9] (RegNegClk[2, 0]): The Negative supply (-3V) regulator needs a 500 kHz clock. A programmable divider

genreates this frequency from the external clock ([15-33] Mhz). Programmation is on 3 bits.

Bits [8, 7] (PrescFactor[1, 0]): used to select the prescaler division factor (see next section: “commutation control”).

Bit 6 (BiasCT): used to bias the spindle centre tap at Vdd5/2 when the spindle outputs are disabled (Run/Stop = 0). The

back-EMF comparator remains operational when BiasCT = 1, to check if the spindle is running for instance.

Bit 5 (Run/Stop): after the power supply is turned on and PorN is high, the motor will start spinning when Run/Stop is

set to ‘1’. The spindle power output starts from state code 0 (see table 3). The motor will stop when this bit is set to ‘0’.

The 3 spindle power outputs are then switched off. No brake is applied.

bit 4 (PllEnable): enables the PLL to improve the speed accuracy.

Bit 3 (Manual): selects the manual commutation mode (Run/Stop bit also needs to be high). When getting out of the

manual mode (=> Manual = ‘0’) and keeping the Run/Stop bit high, the internal commutation block will start from the last

state programmed in manual mode.

Bits [2, 0] (ManCom[2, 0]): control the commutation in manual mode when Run/Stop = 1 & Manual = 1.

BIT\

REG

11

10

987

6

5

43210

0

RegNeg

Clk2

[0]

RegNeg

Clk1

[1]

RegNeg

Clk0

[0]

Presc

Factor1

[0]

Presc

Factor0

[0]

BiasCT

[0]

Run/

Stop

[0]

Pll

Enable

[0]

Manual

[0]

Man

Com2

Man

Com1

Man

Com0

1

StartUp

Delay3

StartUp

Delay2

StartUp

Delay1

StartUp

Delay0

ComDe

Lim3

ComDe

Lim2

ComDe

Lim1

ComDe

Lim0

Watch

Dog3

Watch

Dog2

Watch

Dog1

Watch

Dog0

2

Blank

Delay3

Blank

Delay2

Blank

Delay1

Blank

Delay0

DigOut

Mux

[1]

BdGap

Adj2

[0]

BdGap

Adj1

[0]

BdGAp

Adj0

[0]

VcmRet

SoftRis

Vretract

2

Vretract

1

Vretract

0

3

T_Full

Power2

T_Full

Power1

T_Full

Power0

T_Slow

Ret5

T_Slow

Ret4

T_Slow

Ret3

T_Slow

Ret2

T_Slow

Ret1

T_Slow

Ret0

T_Vcm

Brake2

T_Vcm

Brake1

T_Vcm

Brake0

4

FlyBack

Slope1

FlyBack

Slope0

Shock

Thresh1

Shock

Thresh0

Vcm

Retract

[0]

Vcm

Sleep

[1]

Dac12

Sleep

[1]

RegNeg

Sleep

[1]

Shock

Sleep

[1]

Spin

Sleep

[1]

Reg3v3

Enable

[0]

Temp

Select

[0]

5

Speed

bit14

Speed

bit13

Speed

bit12

PllCur

1

PllCur

0

Dac6

ToVCM

[0]

Dac6

bit5

Dac6

bit4

Dac6

bit3

Dac6

bit2

Dac6

bit1

Dac6

bit0

6

Speed

bit11

Speed

bit10

Speed

bit9

Speed

bit8

Speed

bit7

Speed

bit6

Speed

bit5

Speed

bit4

Speed

bit3

Speed

bit2

Speed

bit1

Speed

bit0

7

Dac12a

bit11

Dac12a

bit10

Dac12a

bit9

Dac12a

bit8

Dac12a

bit7

Dac12a

bit6

Dac12a

bit5

Dac12a

bit4

Dac12a

bit3

Dac12a

bit

Dac12a

bit1

Dac12a

bit0

8

Dac12b

bit11

Dac12b

bit10

Dac12b

bit9

Dac12b

bit8

Dac12b

bit7

Dac12b

bit6

Dac12b

bit5

Dac12b

bit4

Dac12b

bit3

Dac12b

bit2

Dac12b

bit1

Dac12b

bit0

9

Shock

Thresh2

[0]