S71PL129JC0 datasheet(24/153 Pages) SPANSION

24 / 153 page

S71PL129JC0/S71PL129JB0/S71PL129JA0

S71PL129Jxx_00_A8 October 28, 2005

Advance

Info rmation

The device enters the CMOS standby mode when the CE1# or CE#2 and RESET#

pins are both held at VIO ± 0.3 V. (Note that this is a more restricted voltage

range than VIH.) If CE1# or CE#2 and RESET# are held at VIH, but not within VIO

± 0.3 V, the device is in standby mode, but the standby current is greater. The

device requires standard access time (tCE) for read access when the device is in

either of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws ac-

tive current until the operation is completed.

ICC3 in “DC Characteristics” represents the CMOS standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The de-

vice automatically enables this mode when addresses remain stable for tACC +

30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-

trol signals. Standard address access timings provide new data when addresses

are changed. While in sleep mode, output data is latched and always available to

the system. Note that during automatic sleep mode, OE# must be at VIH before

the device reduces current to the stated sleep mode specification. ICC5 in “DC

Characteristics” represents the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading

array data. When the RESET# pin is driven low for at least a period of tRP, the

device immediately terminates any operation in progress, tristates all output

pins, and ignores all read/write commands for the duration of the RESET# pulse.

The device also resets the internal state machine to reading array data. The op-

eration that was interrupted should be reinitiated once the device is ready to

accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held

at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held

at VIL but not within VSS±0.3 V, the standby current is greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would

thus also reset the Flash memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin re-

mains a “0” (busy) until the internal reset operation is complete, which requires

a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/

BY# to determine whether the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing (RY/BY# pin is “1”), the reset

operation is completed within a time of tREADY (not during Embedded Algorithms).

The system can read data tRH after the RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# parameters and to Figure 13

for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins

(except for RY/BY#) are placed in the highest Impedance state

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